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As empresas que possuem um bom sistema de logística reversa conseguem melhorar o nível de serviço, atender aos requisitos desejados pelos clientes, ganhar credibilidade no mercado e obter maior lucratividade. O presente estudo tem como objetivo geral analisar a aplicação do método DMAIC na obtenção de melhorias no processo logístico reverso de pós-consumo de decoders da empresa Beta, que atua nas regiões norte e nordeste do Brasil. Para tal, este trabalho utilizou-se da metodologia do estudo de caso, através da abordagem exploratória-descritiva por meio dos procedimentos de pesquisa bibliográfica e de campo. Em relação a natureza, o estudo classifica-se como qualitativo e quantitativo por usar entrevistas e dados numéricos. Após a definição da rotina ótima de acompanhamento do processo logístico reverso de pós-consumo de decoders na empresa, a pesquisa resultou na criação de um fluxo do processo logístico reverso da empresa estudada e um ganho financeiro real com aplicação da metodologia DMAIC. O estudo durou cerca de três meses, tendo seu início em agosto de 2017 e final em outubro de 2017.

Decoders are one of the significant peripheral components of static random-access memory (SRAM). As the CMOS technology moves towards nano scale regime, the leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm CMOS technology. Leakage power is reduced by employing dual-threshold technique. Dual thresholding is a technique that uses transistors of two different threshold voltages. The technique is implemented in simulation by two methods; first method uses transistors with different threshold voltage and the second method uses substrate biasing to vary the threshold voltage. Row and column decoders are designed and simulated in H-Spice. The leakage power is calculated and compared for both the methods. The NAND gate implemented by Method-1 and Method-2 provides a maximum leakage power savings of 87.67% and 90.81% respectively. The maximum leakage power savings of 96.76% and 98.74% is reported for the row decoder implemented by Method-1 and Method-2 respectively. Similarly, Method-1 gives maximum leakage power savings of 97.09% and Method-2 gives a savings of 99.11% for column decoder. The difference in leakage power savings of Method-1 and Method-at same threshold voltage is 3.14%, 1.98%, and 2.02% for NAND gate, row decoder and column decoder respectively.

U radu je detaljno obrazložena složenost slike i video zapisa. Nadalje, opisan je način rada video kompresije. Ono što se kompresijom želi postići je najbolji razmjer između stupnja kompresije, vremena koje je potrebno da se izvrši i kvaliteta same slike, odnosno videa. Vezano uz video kompresiju, opisane su i razne norme kodiranja videa kao što su H.261, H.263, MPEG-2, MPEG-4 part 2, H.264/AVC, HEVC. Norme koje su trenutno vodeće i u širokoj upotrebi su HEVC i AVC. Uz opisivanje normi, navedeno je i kako svaka norma utječe na prostornu i vremensku redundanciju. U sklopu ovog rada opisane su formule za prostornu i vremensku informaciju. Formule su implementirane u programsko rješenje za analizu prostorne i vremenske informacije koje je detaljno obrazloženo. Analiza se provela na šesnaest testnih video zapisa. This paper describes what image and video complexity is. Moreover, it gives a detailed description of how video compression works. The end-goal of video compression is to find the fine line between compression ratio, the time required for the process to finish and the quality of the image/video. Directly linked with the video compression are video compression standards which have been described in detail in this paper. The two which are leading standards right now are HEVC and AVC. Furthermore, equations for the spatial and temporal information are explained. The formulas have been implemented in the software solution which analyses both spatial and temporal information in the provided videos. This is also shown in the paper. The analysis was carried out on sixteen test videos.

Compared with the bit-wise successive cancellation list (SCL) decoding of polar codes, the node-based Fast SCL decoding significantly reduces the decoding latency by identifying special constituent codes and decoding these in parallel. To further reduce the latency of current Fast SCL decoders, we first propose a fast sequence repetition (SR) node-based SCL (Fast SR-SCL) decoding algorithm, which only involves one type of node in the SCL decoding tree. Furthermore, we employ the adaptive path splitting (APS) strategy to terminate the path splitting in the SR node early, without degrading the error-correcting performance. Numerical results show that for 5G uplink codes with a length of 1024 and rates of 1/4, 1/2, and 3/4, our decoder can deliver the same decoding performance while reducing the average latency by 34.5%, 38.0%, and 39.6% compared with the state-of-the-art Fast SCL decoder for a list size L = 8.

This paper presents a study on the complexity and performance of a decoder architecture for polar codes, which are relevant in the implementation of the 5G New Radio. Considering the importance of low latency communications in some 5G application scenarios, we propose an architecture based on non-binary belief propagation, as this kind of decoding technique is suited to a high level of parallelization w.r.t. standard decoders for this class of codes. Therefore, this architecture con be considered appropriate for the practical implementation of decoders characterized by low latency since it can achieve gains around 50% in the processing time for short codewords (256 bits).

This thesis deals with the development and implementation of error detection and correction algorithms in images, in order to control the quality of produced images at the output of digital decoders. To achieve the objectives of this work, we first study the state-of the-art of the existing approaches. Examination of classically used approaches justified the study of a set of objective methods for evaluating the visual quality of images, based on machine learning methods. These algorithms take as inputs a set of characteristics or metrics extracted from the images. Depending on the characteristics extracted from the images, and the availability or not of a reference image, two kinds of objective evaluation methods have been developed: the first based on full reference metrics, and the second based on no-reference metrics; both of them with non-specific distortions. In addition to these objective evaluation methods, a method of evaluating and improving the quality of the images based on the detection and correction of the defective pixels in the images has been implemented. The proposed results have contributed to refining visual image quality assessment methods as well as the construction of objective algorithms for detecting and correcting defective pixels compared to the various currently used methods. An implementation on an FPGA has been carried out to integrate the models with the best performances during the simulation phase., Cette thèse porte sur le développement et l’implémentation des algorithmes de détection et de correction des erreurs dans les images, en vue de contrôler la qualité des images produites en sortie des décodeurs numériques. Pour atteindre les objectifs visés dans cette étude, nous avons commencé par faire l’état de lieu de l’existant. L’examen critique des approches en usage a justifié la construction d’un ensemble de méthodes objectives d’évaluation de la qualité visuelle des images, basées sur des méthodes d’apprentissage automatique. Ces algorithmes prennent en entrées un ensemble de caractéristiques ou de métriques extraites des images. En fonction de ces caractéristiques, et de la disponibilité ou non d’une image de référence, deux sortes de mesures objectives ont été élaborées : la première basée sur des métriques avec référence, et la seconde basée sur des métriques sans référence ; toutes les deux à distorsions non spécifiques. En plus de ces méthodes d’évaluation objective, une méthode d’évaluation et d’amélioration de la qualité des images basée sur la détection et la correction des pixels défectueux dans les images a été mise en œuvre. Les applications ont contribué à affiner aussi bien les méthodes d’évaluation de la qualité visuelle des images que la construction des algorithmes objectifs de détection et de correction des pixels défectueux par rapport aux diverses méthodes actuellement en usage. Une implémentation sur cartes FPGA des techniques développées a été réalisée pour intégrer les modèles présentant les meilleures performances dans de la phase de simulation.

The increasing demand for fast wireless communications requires sophisticated baseband signal processing. One of the computational intense tasks here is advanced Forward Error Correction (FEC), especially the decoding. Finding efficient hardware implementations for sophisticated FEC decoding algorithms that fulfill throughput demands under strict implementation constraints is an active research topic due to increasing throughput, low latency, and high energy efficiency requirements. This paper focuses on the interesting class of Polar Codes that are currently a hot topic. We present a modular framework to automatically generate and evaluate a wide range of Polar Code decoders, with emphasis on design space exploration for efficient hardware architectures. To demonstrate the efficiency of our framework a very high throughput Soft Cancellation (SCAN) Polar Code decoder is shown that was automatically generated. This decoder is, to the best of our knowledge, the fastest SCAN Polar Code decoder published so far.

Orientador: Gustavo Fraidenraich Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação Resumo: Estatísticas da taxa-soma dos decodificadores Integer Forcing (IF) e outros decodificadores baseados em reticulados para sistemas de Múltipla Entrada e Múltipla Saída (MIMO) são analisadas. Duas aproximações para a taxa-soma de decodificadores lineares são derivadas. A primeira aproximação é baseada no algoritimo Gauss-Lagrange para sistemas com duas antenas no transmissor e receptor (arranjo 2x2) e canais descorrelacionados. A segunda aproximação considera um sistema com um arranjo nxn de antenas, para o caso correlacionado e descorrelacionado e é baseado no segundo teorema de Minkowiski O desempenho de decodificadores IF e Compute and Forward Transform (CFT) são analisados na presença de erro de estimação de canal. Uma aproximação para a taxa-soma média na presença de erros de estimação de canal e canais com realização fixa é derivada. Uma aproximação para a taxa-soma ergódica dos decodificadores IF na presença de canais correlacionados e descorrelacionados também é derivada. Decodificadores lineares IF atraíram atenção significativa devido ao seu potencial de atingir melhor desempenho do que outros decodificadores lineares, especialmente quando as matrizes de canal são aproximadamente singulares. No entanto, uma análise mais profunda de seu desempenho na presença de canais não determinísticos é necessária para que se possa quantificar sua vantagem em relação a decodificadores lineares clássicos e para que se possa corretamente projetar sistemas baseados nestes decodificadores Abstract: The statistics of the sum-rate of Integer Forcing (IF) and other lattice-based Multiple Input Multiple Output (MIMO) systems are analyzed. Two approximations to the achievable sum-rate of the IF linear receiver and their respective analytical probability density functions (PDF) are derived. The first approximation is based on the Gauss-Lagrange algorithm for systems with two antennas at the transmitter and receiver (2x2 arrays) and uncorrelated channels. The second approximation considers an nxn array for both correlated and uncorrelated channels and its derivation is based on Minkowiski's second theorem. The performance of IF and Compute and Forward Transform (CFT) receivers is also analyzed under the presence of channel estimation errors. An approximation to their average sum-rate in the presence of these errors for fixed channel realizations is derived. An approximation to the Ergodic IF sum-rate for correlated and uncorrelated channels is also derived. IF linear receiver has attracted significant attention recently due to their potential to perform better than other linear receivers, especially in the presence of channel matrices that are close to singular. However, a more in-depth analysis of its performance in the presence of non-deterministic channels is necessary in order to quantify its advantage over classical linear receivers and to correctly design systems that rely on these decoders. Another contribution of this work involves blind decoding in Massive MIMO systems. We propose a variation to the fast Independent Component Analysis (fastICA) which takes into consideration the shape of the constellations to obtain better performance Doutorado Telecomunicações e Telemática Doutor em Engenharia Elétrica CAPES

This thesis is focused on the design and implementation of binary low-density parity-check (LDPC) code decoders for high-speed modern communication systems. The basic of LDPC codes and the performance and bottlenecks, in terms of complexity and hardware efficiency, of the main soft-decision and hard-decision decoding algorithms (such as Min-Sum, Optimized 2-bit Min-Sum and Reliability-based iterative Majority-Logic) are analyzed. The complexity and performance of those algorithms are improved to allow efficient hardware architectures. A new decoding algorithm called One-Minimum Min-Sum is proposed. It reduces considerably the complexity of the check node update equations of the Min-Sum algorithm. The second minimum is estimated from the first minimum value by a means of a linear approximation that allows a dynamic adjustment. The Optimized 2-bit Min-Sum algorithm is modified to initialize it with the complete LLR values and to introduce the extrinsic information in the messages sent from the variable nodes. Its variable node equation is reformulated to reduce its complexity. Both algorithms were tested for the (2048,1723) RS-based LDPC code and (16129,15372) LDPC code using an FPGA-based hardware emulator. They exhibit BER performance very close to Min-Sum algorithm and do not introduce early error-floor. In order to show the hardware advantages of the proposed algorithms, hardware decoders were implemented in a 90 nm CMOS process and FPGA devices based on two types of architectures: full-parallel and partial-parallel one with horizontal layered schedule. The results show that the decoders are more area-time efficient than other published decoders and that the low-complexity of the Modified Optimized 2-bit Min-Sum allows the implementation of 10 Gbps decoders in current FPGA devices. Finally, a new hard-decision decoding algorithm, the Historical-Extrinsic Reliability-Based Iterative Decoder, is presented. This algorithm introduces the new idea of considering hard-decision votes as soft-decision to compute the extrinsic information of previous iterations. It is suitable for high-rate codes and improves the BER performance of the previous RBI-MLGD algorithms, with similar complexity., Esta tesis se ha centrado en el diseño e implementación de decodificadores binarios basados en códigos de comprobación de paridad de baja densidad (LDPC) válidos para los sistemas de comunicación modernos de alta velocidad. Los conceptos básicos de códigos LDPC, sus prestaciones y cuellos de botella, en términos de complejidad y eficiencia hardware, fueron analizados para los principales algoritmos de decisión soft y decisión hard (como Min-Sum, Optimized 2-bit Min-Sum y Reliability-based iterative Majority-Logic). La complejidad y prestaciones de estos algoritmos se han mejorado para conseguir arquitecturas hardware eficientes. Se ha propuesto un nuevo algoritmo de decodificación llamado One-Minimum Min-Sum. Éste reduce considerablemente la complejidad de las ecuaciones de actualización del nodo de comprobación del algoritmo Min-Sum. El segundo mínimo se ha estimado a partir del valor del primer mínimo por medio de una aproximación lineal, la cuál permite un ajuste dinámico. El algoritmo Optimized 2-bit Min-Sum se ha modificado para ser inicializado con los valores LLR e introducir la información extrínseca en los mensajes enviados desde los nodos variables. La ecuación del nodo variable de este algoritmo ha sido reformulada para reducir su complejidad. Ambos algoritmos fueron probados para el código (2048,1723) RS-based LDPC y para el código (16129,15372) LDPC utilizando un emulador hardware implementado en un dispositivo FPGA. Éstos han alcanzado unas prestaciones de BER muy cercanas a las del algoritmo Min-Sum evitando, además, la aparición temprana del fenómeno denominado suelo del error. Con el objetivo de mostrar las ventajas hardware de los algoritmos propuestos, los decodificadores se implementaron en hardware utilizando tecnología CMOS de 90 nm y en dispositivos FPGA basados en dos tipos de arquitecturas: completamente paralela y parcialmente paralela utilizando el método de actualización por capas horizontales. Los resultados muestran que los decodificadores propuestos e implementados son más eficientes en área-tiempo que otros decodificadores publicados y que la baja complejidad del algoritmo Modified Optimized 2-bit Min-Sum permite la implementación de decodificadores en los dispositivos FPGA actuales consiguiendo una tasa de 10 Gbps. Finalmente, se ha presentado un nuevo algoritmo de decodificación de decisión hard, el Historical-Extrinsic Reliability-Based Iterative Decoder. Este algoritmo introduce la nueva idea de considerar los votos de decisión hard como decisión soft para calcular la información extrínseca de iteracions anteriores. Este algoritmo es adecuado para códigos de alta velocidad y mejora el rendimiento BER de los algoritmos RBI-MLGD anteriores, con una complejidad similar., Aquesta tesi s'ha centrat en el disseny i implementació de descodificadors binaris basats en codis de comprovació de paritat de baixa densitat (LDPC) vàlids per als sistemes de comunicació moderns d'alta velocitat. Els conceptes bàsics de codis LDPC, les seues prestacions i colls de botella, en termes de complexitat i eficiència hardware, van ser analitzats pels principals algoritmes de decisió soft i decisió hard (com el Min-Sum, Optimized 2-bit Min-Sum y Reliability-based iterative Majority-Logic). La complexitat i prestacions d'aquests algoritmes s'han millorat per aconseguir arquitectures hardware eficients. S'ha proposat un nou algoritme de descodificació anomenat One-Minimum Min-Sum. Aquest redueix considerablement la complexitat de les equacions d'actualització del node de comprovació del algoritme Min-Sum. El segon mínim s'ha estimat a partir del valor del primer mínim per mitjà d'una aproximació lineal, la qual permet un ajust dinàmic. L'algoritme Optimized 2-bit Min-Sum s'ha modificat per ser inicialitzat amb els valors LLR i introduir la informació extrínseca en els missatges enviats des dels nodes variables. L'equació del node variable d'aquest algoritme ha sigut reformulada per reduir la seva complexitat. Tots dos algoritmes van ser provats per al codi (2048,1723) RS-based LDPC i per al codi (16129,15372) LDPC utilitzant un emulador hardware implementat en un dispositiu FPGA. Aquests han aconseguit unes prestacions BER molt properes a les del algoritme Min-Sum evitant, a més, l'aparició primerenca del fenomen denominat sòl de l'error. Per tal de mostrar els avantatges hardware dels algoritmes proposats, els descodificadors es varen implementar en hardware utilitzan una tecnologia CMOS d'uns 90 nm i en dispositius FPGA basats en dos tipus d'arquitectures: completament paral·lela i parcialment paral·lela utilitzant el mètode d'actualització per capes horitzontals. Els resultats mostren que els descodificadors proposats i implementats són més eficients en àrea-temps que altres descodificadors publicats i que la baixa complexitat del algoritme Modified Optimized 2-bit Min-Sum permet la implementació de decodificadors en els dispositius FPGA actuals obtenint una taxa de 10 Gbps. Finalment, s'ha presentat un nou algoritme de descodificació de decisió hard, el Historical-Extrinsic Reliability-Based Iterative Decoder. Aquest algoritme presenta la nova idea de considerar els vots de decisió hard com decisió soft per calcular la informació extrínseca d'iteracions anteriors. Aquest algoritme és adequat per als codis d'alta taxa i millora el rendiment BER dels algoritmes RBI-MLGD anteriors, amb una complexitat similar.

Active error decoding and correction of topological quantum codes - in particular the toric code - remains one of the most viable routes to large scale quantum information processing. In contrast, passive error correction relies on the natural physical dynamics of a system to protect encoded quantum information. However, the search is ongoing for a completely satisfactory passive scheme applicable to locally-interacting two-dimensional systems. Here, we investigate dynamical decoders that provide passive error correction by embedding the decoding process into local dynamics. We propose a specific discrete time cellular-automaton decoder in the fault tolerant setting and provide numerical evidence showing that the logical qubit has a survival time extended by several orders of magnitude over that of a bare unencoded qubit. We stress that (asynchronous) dynamical decoding gives rise to a Markovian dissipative process. We hence equate cellular-automaton decoding to a fully dissipative topological quantum memory, which removes errors continuously. In this sense, uncontrolled and unwanted local noise can be corrected for by a controlled local dissipative process. We analyze the required resources, commenting on additional polylogarithmic factors beyond those incurred by an ideal constant resource dynamical decoder., 8 pages, 3 figures, replaced with published version

Σε αυτή την εργασία μελετάμε τους αλγορίθμους που χρησιμοποιούνται στην αποκωδικοποίηση των LDPC, με έμφαση στους κώδικες του προτύπου 802.11n. Αντιμετωπίζουμε τις δυσκολίες που αντιμετωπίζουν στην υλοποίηση στο υλικό, κυρίως στην εκτέλεση αριθμητικών πράξεων, και προτείνουμε πρακτικές λύσεις. Χρησιμοποιώντας τα αποτελέσματα εκτενών εξομοιώσεων, καταλήγουμε στις βέλτιστες παραμέτρους που θα έχουν οι προτεινόμενες υλοποιήσεις. In this thesis, we study the LDPC decoding algorithms, with emphasis on the 802.11n standard codes. We tackle the hardware implementation difficulties, especially those related to arithmetic computations, and propose practical solutions. Leveraging the results of extensive simulations, we find the optimal parameters of the proposed implementations.