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We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of $7.9 \times 10^{\mathrm {\mathbf {7}}}$ and $4.2 \times 10^{\mathrm {\mathbf {7}}}$ , superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.

In this paper, a new depletion-load metal oxide-based inverter with 3-D structure is realized with film-profile-engineered InGaZnO (IGZO) thin-film transistors (TFTs). The proposed inverter possesses vertically stacked load and drive TFTs whose threshold voltage can be flexibly adjusted into a wide range of −2.3–1 V through merely adjusting the geometric parameters without the necessity of additional processes or masks. The 3-D IGZO inverters constructed through the proposed technology demonstrate full-swing switching with voltage gains up to 19 V/V under an operation voltage of 9 V. The 3-D inverters can not only reduce the footprint but also promote the resistance toward light-induced instability.

By virtue of the film-profile engineering scheme and properly designed device structure, ZnO TFTs with discrete bottom gates and sub-micron channels were fabricated and characterized. In the fabrication, a suspended bridge constructed over the bottom gate is used to tailor the profile of subsequently deposited films. Superior electrical characteristics in terms of ultrahigh ON/OFF current ratio ( $\sim 10^{10}$ ), steep sub-threshold swing ( $66\sim 108$ mV/dec), and very low off-state leakage current are demonstrated with the fabricated devices. Effects of channel lengths on the device characteristics are also explored. Because of more effective shadowing of the depositing species with a longer suspended bridge, the deposited films become thinner at the central channel. As a result, the device shows more positive turn-on voltage and better subthreshold swing with increasing channel length.

In this letter, we demonstrate 0.6- $\mu \text{m}$ ZnON thin-film transistors (TFTs) with the field-effect mobility of 71 cm $^{\mathrm {\mathbf {2}}}$ /V-sec, which to the best of our knowledge is the highest value ever reported on submicrometer oxide–semiconductor TFTs. The drive current, field-effect mobility, and subthreshold slope of ZnON TFTs are significantly improved as compared with their counterpart ZnO TFTs of the same channel dimensions and structure. Such an improvement in the field-effect mobility primarily results from a considerable reduction in the series source/drain (S/D) resistances because of suppression in an interfacial layer formation between Al S/D pads and the channel layer.

$p$ -type SnO thin-film transistors (TFTs) using a nominally symmetrical double-gated (DG) structure were studied in this letter. The top and bottom gates can be biased independently (single-gated mode) or jointly to switch the device (DG mode). For the latter operation, it is shown that ON current, subthreshold swing, and OFF-state current of the SnO TFT are all improved as compared with the operations when only one of the two gates is biased. As the device is operated under the DG mode, field-effect mobility of 6.54 cm2/V-s, high ON/OFF current ratio of $> 10^{5}$ , and subthreshold swing of 143 mV/decade are obtained. Moreover, the capability of the device in tuning its transfer characteristics under the single-gated operation with the bias applied to the opposite gate is also confirmed.

Root cause for the anomalous degradation in the ON-current of film-profile-engineered ZnO thin-film transistors with discrete bottom gates, a new scheme proposed in our previous work, is investigated. Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owing to two TiN wires hung over the S/D regions, which are unintentionally formed during the fabrication of devices. The disconnected S/D metal contacts cause an increase in the S/D series resistance, and thus, the ON-current is degraded. Several ways for addressing this issue are proposed in this letter, including the simple thinning of gate electrode. As the undesirable TiN wires are eliminated, the devices demonstrate enhanced field-effect mobility and uniformity in performance.

We propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE.

IGZO transistors with various gate/drain-offset lengths (L gdo ) were fabricated with the film-profile-engineering method. Breakdown voltage (VBD) of the fabricated devices increases while transconductance (gm) decreases with increasing L gdo . In contrast, threshold voltage and subthreshold swing remain relatively unchanged. V bd of ∼80 V is obtained with L gdo of 0.3 μm. Output characteristics with operation voltage up to 50 V are also demonstrated, evidencing the capability of the device for high-voltage operation. Impact of hot-carrier stress is also investigated in this work.

Short-channel zinc oxynitride (ZnON) thin-film transistors (TFTs) were fabricated based on the film profile engineering in combination with e-beam lithographical patterning. ZnON films were deposited using reactive magnetron sputtering in N 2 /O 2 ambient and exhibit a Hall mobility of 95 cm2/V-s. A ZnON TFT with channel length of 147nm shows high on/off current ratio of 5×107 and field-effect mobility of 9.1 cm2/Vs, which are superior or comparable to their counterparts of IGZO or ZnO TFTs.

Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (G m ). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.

We demonstrate InGaZnO (IGZO) TFTs with channel-length (L) tunable Vth for high-gain BEOL logic gate inverters in a unique film-profile engineering (FPE) approach. In this FPE scheme the thickness and film profile of gate oxide and IGZO active layer are directly tailored by L (0.4–0.8 μm) in a single step, leading to a wide-ranging tunability in Vth of −0.2–+1.6V at no expense of additional masks and process steps. This provides an effective degree of freedom in the layout design for the realization of area-saving, high-gain unipolar logic inverters with load-transistors. Record-high voltage gain of 112 is demonstrated from the unipolar logic inverter with depletion-load 0.4 μm IGZO TFT and 0.7μm IGZO drive-transistor, respectively, at operation voltage (Vdd) of 9V.

This work reports the first experimental submicron and sub-100 nm ZnON TFTs with excellent performance. Field-effect mobility values as high as 55 and 9.2 cm2/V-s were measured from ZnON TFTs with channel lengths of 0.5 μm and 75 nm, respectively. Those are the highest values ever reported on oxide-semiconductor TFTs of comparable channel length. The results confirm ZnON TFTs as an effective building block for the construction of BEOL circuits integrated in a chip.

In this work, we investigate the effectiveness of three organic and inorganic materials as the passivation layers in improving the stability of the a-IGZO devices. Two types of organic materials, FH6400 and Durimide 115A, and inorganic PECVD-SiO X were explored in this work. Because of the effective protection from the diffusion of the gas molecules, especially the oxygen molecules, to the active layer, a-IGZO TFTs with the capping of organic passivation layer show good stability under positive bias stress and also show better stability under light illumination with negative bias stress due to low hydrogen content.

High performance p-type SnO TFTs were fabricated and characterized in this work. Owing to thermal oxygen annealing process, the originally tin-rich oxide film was transformed into a polycrystalline SnO, resulting in decent field-effect mobility and high on/off current ratio. Electrical stability was evaluated by examining the threshold voltage shift under negative bias stresses at different stress times. A scenario considering the passivation/de-passivation of acceptor defects in the channel and the hole trapping of the gate oxide is proposed to explain the observed instability of the SnO TFTs.

We proposed a modified film profile engineering (FPE) process with laminated hardmask (HM) structure to fabricate ZnO thin-film transistors (TFTs) with channel length (L) down to 10 nm. The fabricated ultra-short devices demonstrate uniform and excellent performance. 38 nm ZnO TFTs with discrete TiN gates were also fabricated for suppressing the off-state leakage current.

In this work, we study the impact of gate dielectrics on the characteristics of bottom-gated tin-oxide thin-film transistors annealed in an oxygen ambience at 300 °C for various periods. SiO2, HfO2, and Al2O3 are employed as the gate dielectric in the test devices. The results show that the devices will start exhibiting p-type conduction behavior as the annealing reaches a specific time period which is closely related to the underlying gate dielectric, and the device characteristics can be improved as the annealing proceeds further. Nonetheless, a prolonged annealing may cause degradation of the devices. High hole mobility (3.33 cm2 V−1 s−1), low threshold voltage (1.95 V), and excellent I on/I off ratio (∼104) are achieved on SnO TFTs with a SiO2 gate dielectric after an annealing of 30 min.

In this work, we study the properties of tin oxide films, which were annealed in oxygen ambient for various periods. The as-deposited tin oxides are tin-dominant and, from the Hall measurements, they are of the n-type with high electron concentrations (>1019 cm−3) and would change to the p-type when the oxygen annealing is sufficiently long. We have also found that changes in the structure and crystallinity of the channel layer can be clearly observed by X-ray diffraction analysis and optical microscopy. On the basis of the observations, a physical scheme is proposed to describe the evolution of the electrical performance of oxygen-annealed devices. A hole mobility of 3.24 cm2 V−1 s−1, a subthreshold swing of 0.43 V/dec, a threshold voltage of 1.4 V, and an on/off current ratio larger than 103 are obtained as the channel is transformed into SnO.

In this study we cleverly employ the film profile engineering (FPE) concept to fabricate amorphous InGaZnO (a-IGZO) thin-film transistor (TFT)-based inverters with a resistor- or transistor-load. In the fabrication the profiles of major thin films in both load and drive devices can be properly tailored with designed channel dimensions and deposition conditions. Although the inverter with a resistor-load is simpler in structure and fabrication, the switching performance is found to be restricted by the passive load component. The performance can be greatly promoted as a depletion-mode transistor-load is used instead. Full-swing operation is demonstrated for the inverter with a voltage gain of 28 recorded at an operation voltage (VDD) of 5 V.