80 results on '"Schafer, Benjamin Carrion"'
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2. Implementation of a FPGA-Based Feature Detection and Networking System for Real-time Traffic Monitoring
3. Source Code Obfuscation of Behavioral IPs: Challenges and Solutions
4. VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration
5. Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue
6. S3CBench: Synthesizable Security SystemC Benchmarks for High-Level Synthesis
7. Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs
8. Approximating HW Accelerators through Partial Extractions onto Shared Artificial Neural Networks
9. Optimizing Behavioral Near On-Chip Memory Computing Systems
10. Investigating the Effect of different eFPGAs fabrics on Logic Locking through HW Redaction
11. Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs
12. Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling
13. Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control
14. Special Session: ADAPT: ANN-ControlleD System-Level Runtime Adaptable APproximate CompuTing
15. Functional Locking through Omission: From HLS to Obfuscated Design
16. BEACON: BEst Approximations for Complete BehaviOral HeterogeNeous SoCs
17. Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation
18. Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing
19. Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial Encryptions
20. Watermarking of Behavioral IPs: A Practical Approach
21. Efficient Hierarchical Post-Silicon Validation and Debug
22. Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures
23. Flexible Runtime Reconfigurable Computing Overlay Architecture and Optimization for Dataflow Applications
24. High-Level Synthesis Design Space Exploration: Past, Present, and Future
25. Light-Weight Soft-Errors Detection Mechanism in High-Level Synthesis
26. Predictive Compositional Method to Design and Reoptimize Complex Behavioral Dataflows
27. Bespoke Behavioral Processors
28. Hardware-Assisted Simulation of Voltage-Behind-Reactance Models of Electric Machines on FPGA
29. Efficient Functional Locking of Behavioral IPs
30. DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY
31. Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration
32. Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization
33. On the Design of High Performance HW Accelerator through High-level Synthesis Scheduling Approximations
34. Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models
35. Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration
36. Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration
37. Toward Self-Tunable Approximate Computing
38. Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis
39. Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis
40. Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis
41. Machine Learning to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration.
42. DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY.
43. A machine learning based hard fault recuperation model for approximate hardware accelerators
44. HW/SW co-design experimental framework using configurable SoCs
45. Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic Workloads
46. Configurable SoC In-Situ Hardware/Software Co-Design Design Space Exploration
47. Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level
48. Hardware Trojan Detection in Behavioral Intellectual Properties (IP's) Using Property Checking Techniques
49. Learning-based interconnect-aware dataflow accelerator optimization
50. Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neural Networks. A Case Study
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