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Terrestrial neutron and alpha particle irradiation data for a 7-nm bulk FinFET technology reveal the persisting reliability threat single-event latchup (SEL) poses to advanced technology nodes. SEL is characterized over a wide range of supply voltages and temperatures for this technology node. SEL data is analyzed to determine the holding voltage ( $V_{\mathrm {HOLD}}$ ) required to sustain SEL, which can be as low as 0.85 V at elevated temperatures. Such low SEL holding voltage within 100 mV of nominal supply voltage poses a major reliability threat.

Logic soft-error rates are expected to exceed latch soft-error rates at advanced technology nodes due to operating frequencies in the GHz range. Predictive models for logic soft-errors need difficult-to-obtain data for single-event transient pulse widths. This work proposes an empirical method for estimating logic soft-error rates using shift registers designed with conventional D flip-flops at the 7-nm node. Availability of this model will provide insight to designers on logic soft-error contributions during the design stages.

Integrated circuits are expected to operate across a wide range of temperatures and supply voltages. At the 7-nm FinFET technology node, the self-heating of individual transistors may further increase local temperatures on a die. The combined effects of supply voltage variations and elevated temperatures on soft-error rates for the 7-nm node are investigated. Results show increased sensitivity to soft errors at reduced supply voltage and elevated temperature conditions due to decreased charge collection.

A novel failure mechanism, operating-frequency-triggered latchup-like high-current state, has been observed at the 7-nm bulk FinFET node and is characterized in this paper. Results show that the operating frequency in the GHz range on an IC may lead to a significant increase in the substrate-injection current leading to latchup-like events.

More sensors mean better visibility and subsequently increased systems reliability… up to a point. Additional relevant silicon-based sensors require additional software, test cases, and product costs. In this paper we argue that the cost/benefit balance has shifted towards having more sensors with the advent of telemetry mechanisms to carry the sensor readings and machine learning facilities to low-overhead anomaly detection models and resources. The choice of the sensors to use and their association to high-level function-related sensors has demonstrated that silicon-based sensors in system components add important value on top of high-level function-related sensors, such as root cause analysis; early failure prediction, and system reliability prediction.

Single-Event Transients (SETs) are a dominant determinant of Soft-Error Rates (SER) for CMOS circuits. In this paper, effects of elevated temperature and supply voltages on SET pulse widths are analyzed for a 7-nm bulk FinFET technology for alpha particle exposures. Experimental results indicate that SET pulse widths at the 7-nm node strongly depend on temperature, and the different charge collection mechanisms, including charge drift and charge diffusion, are key factors affecting the SET pulse widths.

Thermal neutron induced soft-errors in 7nm bulk FinFET technology are characterized as a function of supply voltage in this work. Results show that thermal neutron induced FIT rates can be as high as 250% of Alpha FIT rates and 12% of fast-neutron FIT rates. Slope of SER vs supply voltage curves is shown to be a function of particle type (fast neutrons, thermal neutrons, or alpha particles) and flip-flop design.

A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.

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Since FinFET -based circuits have been proven to have better stability at low supply voltages than planar transistor-based circuits, designers are expected to use a wide range of supply voltages for FinFET -based circuits to manage power requirements. Therefore, it is important to investigate the soft error performance over a range of supply voltages. In this work, soft error Failure-in- Time (FIT)rates of D-Flip-Flop (D-FF)designs in 16-nm and 7-nm bulk FinFET technologies are characterized with alpha particle irradiations. Results show that the rate of increase in FIT rates for 7 -nm FF designs are significantly higher, on average, than those for 16-nm FF designs as supply voltage is reduced.

Triple-well designs provide excellent noise isolation in mixed-signal circuits. But the presence of deep-n-well significantly affects Single-Event (SE) response of these circuits. Comparison of dual-well and triple-well designs for recent technologies have shown inconsistent results. This paper presents SE response of dual-well and triple-well flip-flop (FF) designs at the 7-nm bulk FinFET node. Results show dual-well designs have significantly superior SE performance compared to triple-well designs over a wide range of supply voltages and for different particles. TCAD simulations for different depths of p-well show that collected charge increases when the depth of p-well decreases. The shallow p-well in the deep-n-well design results in strong charge confinement leading to increased SE cross sections.

In this paper, a variety of flip-flop (FF) designs fabricated in a commercial 28-nm Fully-Depleted Silicon on Insulator (FDSOI) technology are evaluated for their single-event upset performance with ions and pulsed laser experiments. These FF designs consist of unhardened DFF, hardened DFF with stacked transistors in the inverters, and the layout-optimized DFFs. These DFFs were exposed to alpha particles and heavy ions (HIs). None of the hardened DFFs exhibit any errors up to a Linear Energy Transfer (LET) of 50 MeV*cm2/mg under normal irradiation, and a layout-based hardened DFF started to see errors at a LET of 50 MeV*cm2/mg with the tilt angle of 600. The testing data substantiates effective SEU reduction of these hardened designs. Two-photon absorption (TPA) laser experiments were carried to test these DFF designs, and the results showed that pulsed laser may not be a valid tool to evaluate the FFs designed with nano-scale SOI stacked structures. This brings new challenges in laser hardness assurance for RHBD designs.

In this paper, we present D flip-flop, Quatro, and stacked Quarto flip-flop designs fabricated in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are introduced in the stacked Quatro design to protect the sensitive devices of the original structure. Striking either of the stacked devices will not upset the latch because the conduction path to the supply rail is still cut off by the other off-state device. The irradiation experimental results substantiate that the stacked Quatro design has significantly better SEU tolerance (e.g., higher heavy ion upset Linear Energy Transfer threshold and smaller cross-section data) than the reference designs. It introduces power and area penalties because the proposed design duplicates and stacks two sensitive PMOS devices. Additionally, the impact of technology scaling on Quatro in various technology nodes (130-nm, 65-nm, and 40-nm) has been studied suggesting decreasing upset threshold and decreasing cross-section data.

Two types of clock networks including clock mesh and a buffered clock tree in a daisy-chain style were utilized to synchronize 5 DFF chains and fabricated in a 28 nm bulk CMOS technology. Alpha and proton particles did not trigger any errors indicating the significant single event tolerance of these clock networks. Heavy ion results for the data input pattern of checkerboard (alternate 1 and 0) are presented showing few occurrences of burst errors induced by single event transients (SETs) in the buffered clock tree at relatively high LET values. The same phenomena were observed in laser tests. Clock mesh is therefore proven to be less sensitive to SETs, if pre-mesh drivers do not generate transients. Otherwise, clock mesh possesses lower tolerance, as demonstrated in previous work. Moreover, these burst errors occurred (1) simultaneously in a DFF chain and its subsequent chains, or (2) in a single chain with subsequent chains unaffected. The distinct mechanisms of these burst errors were found to be the electrical masking effect of the daisy-chain clock buffers.

All communications systems use optical modules to achieve data transfer speeds in the 10's of GBPS range. With increasing reliance on communication systems, the impact of soft errors in optical transceiver modules has become a primary concern for system performance. This paper examines neutron-induced soft error rates and associated failure modes of optical transceivers.

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. As a result, grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or nearmore » normal incidence for the bulk circuits.« less

The ambipolar-diffusion-with-cutoff (ADC) model is extended to estimate the single-event-induced collected charge for multiple transistors for circuits simulation. The proposed improvement in the model includes both parasitic-bipolar and charge-sharing effects for a given technology. Simulation results indicate excellent agreement between the proposed model and published TCAD data for 130, 90, 65, and 40 nm technology nodes. A comparison between ADC and both rectangular parallelepiped (RPP) and integral rectangular parallelepiped (IRPP) models indicates a 2.7 × and 2.5 × lower error in estimating collected charge when compared with TCAD data. The ADC average error was estimated to be 7.1 fC and for the RPP and IRPP about 19.1 fC and 17.5 fC, respectively, across the technologies for particles with the linear energy transfer range from 1 - 30 MeV-cm 2 /mg.

This paper presents an SEU-tolerant Dual Interlocked Storage Cell (DICE) latch design with both PMOS and NMOS transistors in the feedback paths. The feedback transistors improve the SEU tolerance by increasing the feedback loop delay during the hold mode. The latch design was implemented in a shift register fashion at a 130-nm bulk CMOS process node. Exposures to heavy-ions exhibited a significantly higher upset LET threshold and lower cross-section compared with the traditional DICE latch design. Performance penalties in terms of write delay, power, and area are non-significant compared to traditional DICE design.

Soft-error rates (SER) of Flip-Flop (FF) designs in a 16-nm bulk FinFET technology are characterized with thermal neutron, high-energy neutron and alpha particle irradiations. Results show that the contribution of thermal-neutron-induced SER can be higher or lower than alpha-particle-induced SER for different FF designs and can be comparable to high-energy-neutron-induced SER for some FF designs. The contribution of thermal-neutron-induced SER to overall SER can be significantly higher than previously reported.

With designers employing FF hardening techniques to mitigate soft errors in complex ASICs, low-cost controller ICs have become one of the most vulnerable parts at the system-level. In this paper, SSD controllers are evaluated for neutron soft error performance to estimate their vulnerability. Results show such ubiquitous controller ICs contribute significantly to the system-level SER.

This is a prospective, naturalistic study to evaluate patient’s report on sleep and depression in early recovery while receiving buprenorphine in Medication Assisted Treatment (MAT). 40 Subjects entering into MAT with buprenorphine/naloxonefor opioid dependence disorder were recruited. No change of concurrent treatment was made. Subjects were administered Sleep Scale from the Medical Outcomes Study (MOS-Sleep), a 5-item Supplemental Sleep Scale (SSS), and the Beck Depression Inventory II (BDI-II). The measures were administered at day 0 (baseline), 30, 60 and 90 days. The result showed that patients reported significant progressive improvements in three MOS-Sleep subscales: sleep disturbance, sleep indices I and II. The mean scores of SLPD4 (Sleep disturbance) at day 0, 30, 60, 90 were 62.4, 53.2, 53.3, and 48.4 respectively (p=0.0029). Similarly, subscores of SLP6 (Sleep Problem Index I) and SLP 9 (Sleep Problem Index II) were also significantly decreased over time (P=0.038 for SLP6 and p=0.007 for SLP9). BDI-II depression scores improved from “Moderate depression” at baseline to “Mild depression”. The mean BDI score decreased from 24.2 to 17.0 after 90 days of treatment. Findings suggest that subjects reported improvement in both sleep and depression after initiating MAT with buprenorphine/naloxone.

Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.

In this paper a methodology to predict single-event transient (SET) pulse characteristics is proposed. Analytical models and technology pre-characterization are used to estimate SET pulse-widths for different standard cells. The model uses graph analysis of the cell netlist to identify similar circuit structures for reduced computational complexity for the characterization of standard cells. The error between the proposed model and simulations is between 3% and 9.3%. Model predictions are also compared with results from heavy-ion experiments for a test chip fabricated at the 65-nm technology node showing excellent agreement. The proposed model will allow designers to model effects of soft errors at the circuit-level during the design phase.

In this work, the efforts of an industry wide consortium to characterize the logic soft error rate of a multitude of combinational and sequential logic circuits across multiple technologies is reported. The basic intent of the approach was to bring together the designs and intellectual property of various semiconductor companies on a single technology platform to be tested and compared under the same experimental conditions. This ensures that the measured results are validated, comparable and benchmarked against other similar designs. More importantly, crucial findings associated with this collaborative effort are also outlined in this paper. Some of the key results include the fact that scaling has led to the steady decline of failure in time (FIT) rates for flip-flops as well as combinational logic circuits. Additionally, the improvement in the soft error resilience provided by redundant node flip-flops has reduced with technology miniaturization due to the effects of charge sharing and multiple node charge collection. In spite of this, however, at high frequencies, the combinational logic soft error rate is comparable to the soft error rate of typical flip-flops. The experimental results are complemented with modeling various soft error mechanisms that affect modern high speed logic circuits.