Search

Bulk 14-nm FinFET technology was irradiated in a heavy-ion environment (42-MeV Si ions) to study the possibility of displacement damage (DD) in scaled technology devices, resulting in drive current degradation with increased cumulative fluence. These devices were also exposed to an electron beam, proton beam, and cobalt-60 source (gamma radiation) to further elucidate the physics of the device response. Annealing measurements show minimal to no “rebound” in the ON-state current back to its initial high value; however, the OFF-state current “rebound” was significant for gamma radiation environments. Low-temperature experiments of the heavy-ion-irradiated devices reveal increased defect concentration as the result for mobility degradation with increased fluence. Furthermore, the subthreshold slope (SS) temperature dependence uncovers a possible mechanism of increased defect bulk traps contributing to tunneling at low temperatures. Simulation work in Silvaco technology computer-aided design (TCAD) suggests that the increased OFF-state current is a total ionizing dose (TID) effect due to oxide traps in the shallow trench isolation (STI). The significant SS elongation and ON-state current degradation could only be produced when bulk traps in the channel were added. Heavy-ion irradiation on bulk 14-nm FinFETs was found to be a combination of TID and DD effects. [ABSTRACT FROM AUTHOR]

We are presenting single-event effect testing results on a 22-nm fully depleted silicon-on-insulator test chip from GlobalFoundries. The 128-Mb static random access memory (SRAMs) were irradiated with heavy ions, and the results are compared to previous partially depleted technology generations (32 and 45 nm). The per-bit cross section is approximately an order of magnitude lower than the previous generations with a higher onset linear energy transfer (LET). No dependence on roll angle or input pattern was found. Tilt angle data follow the cosine law. Increasing the SRAM array supply voltage from the minimum tested 0.73 V to the maximum 1.08 V decreases SEE sensitivity by as much as 8%. Decreasing the p-well voltage from the nominal 0 V to the maximum −2 V increases the SEE cross section by as much as 2 ×. The n-well voltage has little effect on the SEE sensitivity due to the specifics of the transistor layout in the SRAM. Changing both the n- and p-well voltages simultaneously results in identical results as when only the p-well voltage was changed. [ABSTRACT FROM AUTHOR]