128 results on '"Massengill, L. W."'
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2. In Situ Measurement of TID-Induced Leakage Using On-Chip Frequency Modulation
3. Analysis of Single-Event Transients (SETs) Using Machine Learning (ML) and Ionizing Radiation Effects Spectroscopy (IRES)
4. Single-Event Latchup in a 7-nm Bulk FinFET Technology
5. Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI
6. Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology
7. Ionizing Radiation Effects Spectroscopy for Analysis of Single-Event Transients
8. Empirical Modeling of FinFET SEU Cross Sections Across Supply Voltage
9. Exploiting SEU Data Analysis to Extract Fast SET Pulses
10. Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies
11. Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology
12. A Bias-Dependent Single-Event-Enabled Compact Model for Bulk FinFET Technologies
13. Ionizing Radiation Effects Spectroscopy for Analysis of Total-Ionizing Dose Degradation in RF Circuits
14. Dual-Interlocked Logic for Single-Event Transient Mitigation
15. Power-Aware SE Analysis of Different FF Designs at the 14-/16-nm Bulk FinFET CMOS Technology Node
16. Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation
17. Effects of Total-Ionizing-Dose Irradiation on Single-Event Response for Flip-Flop Designs at a 14-/16-nm Bulk FinFET Technology Node
18. Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology
19. Designing soft-error-aware circuits with power and speed optimization
20. Impact of supply voltage and particle LET on the soft error rate of logic circuits
21. Predicting Muon-Induced SEU Rates for a 28-nm SRAM Using Protons and Heavy Ions to Calibrate the Sensitive Volume Model
22. Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques
23. The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops
24. Frequency Dependence of Heavy-Ion-Induced Single-Event Responses of Flip-Flops in a 16-nm Bulk FinFET Technology
25. Exploiting Parallelism and Heterogeneity in a Radiation Effects Test Vehicle for Efficient Single-Event Characterization of Nanoscale Circuits
26. An Empirical Model for Predicting SE Cross Section for Combinational Logic Circuits in Advanced Technologies
27. Time-Domain Modeling of All-Digital PLLs to Single-Event Upset Perturbations
28. Persistent Laser-Induced Leakage in a 20 nm Charge-Pump Phase-Locked Loop (PLL)
29. Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process
30. Analysis of TID Process, Geometry, and Bias Condition Dependence in 14-nm FinFETs and Implications for RF and SRAM Performance
31. Combined Effects of Total Ionizing Dose and Temperature on a K-Band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology
32. Estimating Single-Event Logic Cross Sections in Advanced Technologies
33. Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs
34. Probability of latching an SET in advanced technologies
35. Estimation of single-event transient pulse characteristics for predictive analysis
36. Predicting the vulnerability of memories to muon-induced SEUs with low-energy proton tests informed by Monte Carlo simulations
37. SE performance of a Schmitt-trigger-based D-flip-flop design in a 16-nm bulk FinFET CMOS process
38. Hardware based empirical model for predicting logic soft error cross-section
39. Influence of Voltage and Particle LET on Timing Vulnerability Factors of Circuits
40. Radiation Hardening of Voltage References Using Chopper Stabilization
41. Estimation of Single-Event-Induced Collected Charge for Multiple Transistors Using Analytical Expressions
42. Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology
43. Multi-Cell Soft Errors at Advanced Technology Nodes
44. Single-Event Characterization of Bang-bang All-digital Phase-locked Loops (ADPLLs)
45. The Contribution of Low-Energy Protons to the Total On-Orbit SEU Rate
46. Heavy Ion SEU Test Data for 32nm SOI Flip-Flops
47. Multi-cell soft errors at the 16-nm FinFET technology node
48. Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors
49. Irradiation and Temperature Effects for a 32 nm RF Silicon-on-Insulator CMOS Process
50. Single-Event Transient Induced Harmonic Errors in Digitally Controlled Ring Oscillators
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