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Dynamic random access memories (DRAMs) are currently used as the core memory in computing systems because of their high speed and density. Their demand should continue to grow owing to increased data usage. A unit cell in a DRAM consists of one transistor and one capacitor, and the data are stored in the capacitor. As the size of the unit cell decreases to improve the memory density by aggressive scaling, it is important to secure sufficient capacitance in the capacitor. In this regard, technological advances in the fabrication of capacitors are of great importance; accordingly, the materials and processing of high‐k thin films require developmental innovations. Besides, it is necessary to develop electrode materials that optimize the function of high‐k thin films. In this review, recent advances in achieving sufficient capacitance in DRAM capacitors are summarized from structural and material/process perspectives, and the future direction of DRAM capacitor development is discussed. Atomic layer deposition (ALD) is a key technique that enables the growth of functional thin films for DRAM capacitors; thus, recent advances in the deposition of high‐k and electrode thin films grown using the ALD technique are addressed. [ABSTRACT FROM AUTHOR]

The interface between a dielectric thin film and a metal electrode is studied to improve reliability as well as electrical properties of the metal–insulator–metal (MIM) capacitor in dynamic random‐access memory (DRAM) devices. The interfacial layers between a dielectric thin film and a metal electrode play important functional roles such as increasing the electrical barrier or preventing oxygen defects in high‐k dielectrics. By introducing an electrical barrier layer or a sacrificial layer at the metal–dielectric interface for engineering the electronic band, lattice, or dipole, various effects could be confirmed such as the conduction band offset (CBO), bandgap or mismatch modulation for controlling the dielectric loss depending on the AC frequency or leakage current of MIM capacitors. Upon the insertion of Al2O3 as an electrical barrier layer, CBO increased because of the band engineering. Further, upon the insertion of TiO2 as a sacrificial layer at the interface, CBO increased because of the dipole formation at the interface, attributed to the difference in electronegativity. Thus, a robust MIM capacitor for DRAM that maintains a low leakage current and has improved reliability which is realized using the proper combination of interfacial layers. [ABSTRACT FROM AUTHOR]

The continuous scale-down of dynamic random-access memory (DRAM) requires shrinkage of high aspect ratio metal-insulator-metal (MIM) capacitance along with the successful suppression of its leakage current to maintain desired levels of charge storage and retention. As the dimensions of stacked insulating dielectric and metal electrodes in the MIM capacitor are currently <10 nm, interfacial mixing has a large impact on the reliability of the capacitor. This is because defects and secondary interface oxides significantly alter the physicochemical properties of MIM capacitors. The methodology required to characterize ultrathin interfaces in relation to the performance of MIM devices is highly challenging due to its physical and chemical complexities of interface between dielectric and electrode. In this study, a ZrO2-based dielectric film and its interface (with an ultrathin TiO2/Al2O3 buffer layer) are analyzed using angle-resolved X-ray photoelectron spectroscopy (ARXPS), spectroscopic ellipsometry (SE), and temperature dependent I–V analysis for a DRAM MIM capacitor. The composite dielectric layer included either Al2O3 on the bottom or Al2O3/TiO2 between the TiN electrode and ZrO2. This study suggests an effective metrology approach to characterize ultrathin MIM capacitors and the important role of interfacial stabilization using a buffer layer for the effective control of leakage current. [ABSTRACT FROM AUTHOR]

Background: There are significant variations in the anatomy of the dorsal cutaneous branch of the ulnar nerve (DCBUN). The DCBUN is at risk for iatrogenic injury during surgeries around the ulnar side of the wrist. The purpose of this study was to demonstrate the relationship between the ulnar styloid process and the DCBUN and to confirm the DCBUN's change in location with different forearm positions., Methods: We examined 9 fresh frozen cadaveric limbs to establish the course of this nerve. The DCBUN was dissected and traced around the ulnar border of the wrist. The distance from the tip of the ulnar styloid process to the origin of the DCBUN was measured. The distances from the ulnar styloid process to the DCBUN were measured in supination, pronation, and in a neutral position of the forearm., Results: The DCBUN originated on average 4.92 cm proximal to the ulnar styloid process. In all cases, the DCBUN crossed the ulnar distal to ulnar styloid process and it moved more closely to the ulnar styloid process with a forearm position change from supination to pronation., Conclusions: We recommend making a skin incision on the ulnar side around the styloid process with the forearm in supination or neutral position was another method to avoid injury of DCBUN.