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With continually growing adoption of FPGA based designs, and more features and capabilities available in FPGAs, board and system level test applications can - and should - take advantage of FPGA embedded instrumentation. Such FPGA assisted tests not only improve manufacturing test but also allow extensive testing in the field to address issues such as no-fault-found syndrome by enabling the detection of environment-induced defects or latent defects (related to bad solder joint quality, aging, etc.). In this paper we are briefly reviewing different types of FPGA embedded instruments before specifically addressing synthetic instrumentation and focusing on example use cases. We will be discussing design for test considerations, quality of test and diagnostics, savings in test time and test cost, and levels of automation previously not associated with functional and performance / stress test development.

In this paper, we demonstrate a clear gap in board level test coverage under category of timing related faults (TRFs). Although there are techniques that are capable to detect TRFs, there is no fault coverage metrics to quantify the quality of these techniques. To do that, we propose an easy-to-implement interconnect-level fault model extension towards TRFs. This extension can be integrated into existing test coverage models providing additional information on coverage of timing-related faults.

This paper presents a method for optimization of board-level scan-test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra HW cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant overall test time reduction in comparison with traditional Boundary Scan approach.

A method is proposed for simulating of transition delay faults (TDF) at different fault propagation conditions. The main idea of the method is to extend the TDF model, traditionally considered as a class of robustly tested delay faults, to a class of TDFs with extended detection conditions like non-robust and functional sensitization. A new sensitization type, called nonrobust functional sensitization was introduced as well. A novel delay fault reasoning algorithm based on sequential 7-valued algebra is presented, which is used for fault coverage calculation separately for all mentioned four types of TDFs. By experimental results we established that the fault coverage share for different types of TDFs considerably depends on the quality of delay test.