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Pipeline analog-to-digital converters (ADCs) are typically chosen for medium-to-high-resolution and high-bandwidth applications. Nevertheless, each generation of technology scaling, strongly driven by the demand for even more powerful digital computation capabilities, continuously entails a great challenge on the precision of the interstage gain in pipeline ADCs. The inaccurate interstage gain leads to the quantization leakage error in pipeline ADCs, which degrades the signal-to-noise-and-distortion ratio (SNDR) of pipeline ADCs. This dissertation demonstrates three techniques to address the inaccurate interstage gain in pipeline ADCs. To start with, an interstage gain error shaping (GES) technique is proposed. It can substantially suppress the in-band quantization leakage error in pipeline ADCs. It works for both closed-loop and open-loop amplification. It does not require extra clock phases, long convergence time, or an interruption of the digitization, incur large power or area overhead, or pose a constraint on the input signal. A two-stage pipeline successive-approximation-register (SAR) ADC equipped with the proposed second-order GES technique in 40-nm low-power (LP) CMOS technology achieves a 75.8-dB SNDR over 12.5-MHz bandwidth while operating at 100 MS/s and consuming 1.54 mW. It achieves a 174.9-dB Schreier figure of merit (FoM). The GES-related hardware only occupies less than 2% of the total active area. Next, an enhanced interstage GES technique that adopts a digital error feedback (DEF) method to address the truncation error in the prior implementation is proposed, which can extend the interstage gain error tolerance by five times. The proposed DEF technique does not introduce additional errors as it operates purely in the digital domain. In addition, a first-order passive quantization noise shaping (NS) technique that reduces the input-pair ratio of the two-input-pair comparator by 2.7 times is proposed. The proposed passive NS technique can alleviate the noise penalty caused by using a multiple-input-pair comparator. A two-stage pipeline SAR ADC equipped with the proposed techniques in 40-nm LP CMOS technology achieves a 77.1-dB SNDR over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. It achieves a 173.7-dB Schreier FoM. Finally, the use of foreground interstage gain calibration is demonstrated to address the inaccurate interstage gain in pipeline ADCs. It is implemented in a 13-bit 40-MS/s two-stage pipeline SAR ADC. The prototype ADC is designed for the phase-II readout electronics of the ATLAS liquid argon (LAr) calorimeter. To ensure its robustness under the harsh radioactive environment, several radiation-hardened techniques are implemented. To increase its yield, foreground digital-to-analog converter (DAC) mismatch calibration is also implemented. It is implemented in 65-nm LP CMOS technology. With the foreground calibration, it achieves an effective number of bits (ENOB) better than 11.2 bits over the bandwidth of interest while consuming 17.6 mW. Besides, on-chip high-speed reference buffers are deployed to avoid the need for large decoupling capacitors and provide stable reference voltages by tracking bandgap voltage references.