Search

The floating gate devices, as a kind of nonvolatile memory, obtain great application potential in logic-in-memory chips. The 2D materials have been greatly studied due to atomically flat surfaces, higher carrier mobility, and excellent photoelectrical response. The 2D ReS 2 flake is an excellent candidate for channel materials due to thickness-independent direct bandgap and outstanding optoelectronic response. In this paper, the floating gate devices are prepared with the ReS 2 /h-BN/Gr heterojunction. It obtains superior nonvolatile electrical memory characteristics, including a higher memory window ratio (81.82%), tiny writing/erasing voltage (±8 V/2 ms), long retention (>1000 s), and stable endurance (>1000 times) as well as multiple memory states. Meanwhile, electrical writing and optical erasing are achieved by applying electrical and optical pulses, and multilevel storage can easily be achieved by regulating light pulse parameters. Finally, due to the ideal long-time potentiation/depression synaptic weights regulated by light pulses and electrical pulses, the convolutional neural network (CNN) constructed by ReS 2 /h-BN/Gr floating gate devices can achieve image recognition with an accuracy of up to 98.15% for MNIST dataset and 91.24% for Fashion-MNIST dataset. The research work adds a powerful option for 2D materials floating gate devices to apply to logic-in-memory chips and neuromorphic computing., (© 2024 Wiley‐VCH GmbH.)

The effects of total ionizing dose on 3-D NAND floating gate cells with vertical architecture are analyzed as a function of the cell depth in the pillar. The focus of this work is on TID-induced threshold voltage shifts, but the implications on the raw bit error rates are also discussed. Underlying mechanisms are elucidated, concluding that due to the manufacturing process and the geometry of the pillars, the effects of total dose are larger at the bottom than at the top of the cell array. [ABSTRACT FROM AUTHOR]

Floating gate cells in advanced NAND Flash memories, with single-level and multi-level cell architecture, were exposed to low-energy proton beams. The first experimental evidence of single event upsets by proton direct ionization in floating gate cells is reported. The dependence of the error rate versus proton energy is analyzed in a wide energy range. Proton direct ionization events are studied and energy loss in the overlayers is discussed. The threshold LET for floating gate errors in multi-level and single-level cell devices is modeled and technology scaling trends are analyzed, also discussing the impact of the particle track size. [ABSTRACT FROM PUBLISHER]