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Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses., To be presented 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018); Torino, Italy; October 2018

This paper reports the use of Laser-induced Forward Transfer (LIFT) technology for printing of multilayer flexible circuitries and the fabrication of micro-bumps for flip-chip bonding of packaged LEDs and bare die microcomponents. Bonding of passive and functional surface mount devices (SMD) on low-temperature polyethylene terephthalate (PET) foils have been demonstrated using two selective bonding techniques. Firstly, using a high intensity near-infrared (NIR) lamp, a bare die NFC chip was bonded on micro-bumps formed with LIFT printed isotropic conductive adhesive (ICA) within less than a minute. Secondly, using a high intensity Xenon lamp, passive components and packaged LEDs were bonded within 5 seconds on microbumps formed with conventional Sn-Ag-Cu (SAC) lead-free alloys. In the both cases, due to selective light absorption, a limited temperature increase was observed in the PET substrates allowing successful bonding of components onto the delicate polyethylene foil substrates using conventional interconnect materials. © 2018 IEEE.

In this case study, we investigated the minimum line width and spacing for roll-to-roll (R2R) screen printed silver interconnections on polyethylene terephthalate (PET). This initial pilot investigation involved rotary screen printing 16 high density I/0 patterns while alternating pitch (150, 175, 200, and 250 µm) and nominal screen linewidth (50, 75, 100, 150 µm). Based on those results, we chose the Asahi silver nanoparticle ink and StorkS305 screen to compare three printed chip bonding test patterns utilizing a nominal line width of 75 µm (average printed line width was 115 µm), and a pitch of 150, 175 or 200 µm. Flip chip bonding of daisy chain bare dies was used to compare the effect of gold stud bumping and the choice of anisotropic conductive adhesive (ACA). Even though gold stud bumps ensured reliable connections, the choice of the ACA for unbumped chips proved uncertain, which has provoked ongoing and future investigations.The results of this study shed significant and valuable light on high throughput R2R fabricated hybrid systems and necessary steps to be considered for future high density rotary screen printed hybrid electronic applications.

In this work, low thermal-mass LEDs (LTM-LEDs) were developed and demonstrated in flip-chip configuration, studying both experimentally and theoretically the enhanced electrical and optical characteristics and the limits. LTM-LED chips in 25 × 25 μm2, 50 × 50 μm2, 100 × 100 μm2 and 200 × 200 μm2 mesa sizes were fabricated and comparatively investigated. Here it was revealed that both the electrical and optical properties are improved by the decreasing chip size due to the reduced thermal mass. With a smaller chip size (from 200 μm to 50 μm), the device generally presents higher current density against the bias and higher power density against the current density. However, the 25 × 25 μm2 device behaves differently, limited by the fabrication margin limit of 10 μm. The underneath mechanisms of these observations are uncovered, and furthermore, based on the device model, it is proven that for a specific flip-chip fabrication process, the ideal size for LTM-LEDs with optimal power density performance can be identified. ASTAR (Agency for Sci., Tech. and Research, S’pore) Accepted version

An application-oriented integration concept for a half-bridge switch assembly has been developed based on the latest generation 70- ?m-thin insulated gate bipolar transistors and diodes, which are rated at 600 V/200 A. This paper addresses the design and reliability of the assembly, with a fully bondwireless approach using cylindrical copper bumps. Advanced numerical structural simulation techniques are also applied to assess the influence of interconnect characteristics (material, size, and shape) and try to determine an optimum solution for reducing the stress and creep strain development in the solder joint. Preliminary experimental tests of the power module are also carried out at different switching frequency and loads to prove the validity of the proposed solution in terms of electromagnetic performance.