Search

The computing capacity demanded by embedded systems is on the rise as software implements more functionalities, ranging from best-effort entertainment functions to performance-guaranteed safety-related functions. Heterogeneous manycore processors, using wormhole mesh (wmesh) Network-on-Chips (NoCs) as the main communication means, and contention block among applications, are increasingly considered to deliver the required computing performance. Most research efforts on software timing analysis have focused on deriving bounds (estimates) to the contention that tasks can suffer when accessing wmesh NoCs. However, less effort has been devoted to an equally important problem, namely, accurately measuring the actual contention tasks generate each other on the wmesh which is instrumental during system validation to diagnose any software timing misbehavior and determine which tasks are particularly affected by contention on specific wmesh routers. In this article, we work on the foundations of contention measuring in wmesh NoCs and propose and explain the rationale of a golden metric , called task PairWise Contention (PWC). PWC allows ascribing the actual share of the contention a given task suffers in the wmesh to each of its co-runner tasks at packet level. We also introduce and formalize a Golden Reference Value (GRV) for PWC that specifically defines a criterion to fairly break down the contention suffered by a task among its co-runner tasks in the wmesh. Our evaluation shows that GRV effectively captures how contention occurs by identifying the actual core (task) causing contention and whether contention is caused by local or remote interference in the wmesh.

An increasing number of critical functionalities integrated in embedded critical systems rely on deep learning (DL) technology. This article summarizes certain key aspects of DL’s intrinsic stochastic and training-data-dependent nature that are at odds with current domain-specific functional safety standards. We exemplify how redundancy and diversity of neural networks can help to reconcile DL technology and functional safety requirements. The research leading to these results has received funding from the European Research Council (ERC) grant agreement No. 772773 (SuPerCom), the Horizon Europe Programme under the SAFEXPLAIN Project (www.safexplain.eu), grant agreement num.101069595, and the Spanish Ministry of Science and Innovation under grant PID2019-107255GBC21/AEI/10.13039/501100011033.

The need for increased application performance in high-integrity systems like those in avionics is on the rise as software continues to implement more complex functionalities. The prevalent computing solution for future high-integrity embedded products are multi-processors systems-on-chip (MPSoC) processors. MPSoCs include CPU multicores that enable improving performance via thread-level parallelism. MPSoCs also include generic accelerators (GPUs) and application-specific accelerators. However, the data processing approach (DPA) required to exploit each of these underlying parallel hardware blocks carries several open challenges to enable the safe deployment in high-integrity domains. The main challenges include the qualification of its associated runtime system and the difficulties in analyzing programs deploying the DPA with out-of-the-box timing analysis and code coverage tools. In this work, we perform a thorough analysis of vector extensions (VExt) in current COTS processors for high-integrity systems. We show that VExt prevent many of the challenges arising with parallel programming models and GPUs. Unlike other DPAs, VExt require no runtime support, prevent by design race conditions that might arise with parallel programming models, and have minimum impact on the software ecosystem enabling the use of existing code coverage and timing analysis tools. We develop vectorized versions of neural network kernels and show that the NVIDIA Xavier VExt provide a reasonable increase in guaranteed application performance of up to 2.7x. Our analysis contends that VExt are the DPA approach with arguably the fastest path for adoption in high-integrity systems. This work has received funding from the the European Research Council (ERC) grant agreement No. 772773 (SuPerCom) and the Spanish Ministry of Science and Innovation (AEI/10.13039/501100011033) under grants PID2019-107255GB-C21 and IJC2020-045931-I.

The trend toward the adoption of a multiprocessor system on a chip (MPSoC) in critical real-time domains, like avionics or automotive, responds to the demand for increased computing performance to support advanced software functionalities. The other side of the coin is that MPSoCs challenge software timing analysis. This is so as co-running applications affect each other’s timing behavior on account of the interference incurred when accessing shared hardware resources, with the latter steadily increasing in number and complexity in every new generation of MPSoCs. For a solid and cost-contained software-timing validation approach, we contend that a taxonomy has to be developed to capture the different levels at which processors’ resources can be shared. Those levels are to be related to the conventional run-time software abstractions (e.g., task, thread, runnable) and the particular abstraction used to carry out contention analysis. From the standpoint of contention analysis, only the resources in those levels shared by the different run-time software entities need to be mastered and addressed by timing analysis, whereas the remaining resources can be safely disregarded. We tailor this approach to two of NVIDIA’s embedded platforms, TX2 and AGX Xavier, of particular relevance for the automotive domain. For the identified shared resources, we also characterize the contention that tasks can suffer and discuss the limitations and early approaches for modeling timing interference in shared hardware resources. This work has been partially supported by the SpanishMinistry of Science and Innovation under grants PID2019-107255GB and FJCI-2017 -34095; and the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 878752 (MASTECS) and the European Research Council (ERC) grant agreement No. 772773 (SuPerCom).