1. Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices.
- Author
-
Lacord, J., Martinie, S., Rozeau, O., Jaud, M.-A., Barraud, S., and Barbe, J. C.
- Subjects
ELECTRIC capacity ,PERMITTIVITY ,DIELECTRIC properties ,SILICON ,NANOWIRES - Abstract
In this paper, we propose an analytical model to accurately evaluate the parasitic capacitances of an advanced 7-nm-node multigate device structure: 1) FinFET on Silicon On Insulator (SOI) (FFSOI) and 2) stacked nanowire on SOI (SNWSOI). Our model, validated through 3-D TCAD simulations, accounts for gate contact, advanced process bricks, such as gate last, BAR contact, and low- $k$ spacer, but also multilayer dielectric by introducing an equivalent permittivity. Finally, FFSOI and SNWSOI architectures are compared from this parasitic capacitance point of view. [ABSTRACT FROM AUTHOR]
- Published
- 2016
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