Search

An ultra‐low quiescent current tri‐mode DC–DC boost converter is proposed in this paper, which can efficiently handle loads from 1 μA to 300 mA, providing 5‐V output from 3 to 4.2‐V input. Hysteresis current mode control is adopted to realize seamless mode switching between continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In order to deal with the light load situation, this paper proposes a quasi burst mode (QBM). In this mode, most of the modules are turned off and only the QBM controller, low‐power current bias and sample and hold circuit are retained, which significantly reduces the static current of the converter, and thus improves the light load efficiency. Meanwhile, the average current of error amplifier and comparator are reduced significantly by dynamic biasing. Finally, the efficiency of the converter is greatly improved and kept at a reasonable output ripple. The proposed converter is implemented in a 0.13‐μm BCD process design and manufacturing. The test results show that the quiescent current of the converter is only 780 nA, which can achieve a peak efficiency of 95.6%, and ensure that the efficiency is maintained above 80% in the load range of 10 μA to 300 mA. [ABSTRACT FROM AUTHOR]

In order to achieve high efficiency in a wider load range, a PWM/PFM/Power-Saved mode dc–dc buck converter is proposed. The mode switching technique is based on an accurate power loss model consisting of critical components/parameters: The size of the power transistor and the ON/OFF status of power-hungry subcircuits. The circuit of mode switching technique is achieved by the reference, pulse skipped modulation (PSM) comparator and feedback resistors, and its own consumption of quiescent current is extremely low. At ultra-light load, by detecting the ZCD duration and the ripple of the output, the system can switch to the Power-Saved-Mode. The proposed buck converter was implemented by using a 0.18 μ m CMOS process. It achieves a peak efficiency of 97% and > 90% efficiency from 100 μ A to 600 mA. A 360 nA quiescent current is achieved. With a low output ripple of less than 60 mV, the input voltage range and regulated output voltage are 3.6–5 V and 1.2–3.3 V, respectively. [ABSTRACT FROM AUTHOR]

In this paper, an improved voltage-mode constant on-time (COT) control DC–DC buck converter is designed, which makes the DC–DC buck converter have good stability. Firstly, an improved compensation scheme is introduced through the analysis and derivation of the traditional voltage-mode COT controlled buck converter model. Then, according to the application requirements of the design, Simplis software modeling is used to verify the correctness of the theoretical analysis. The 0.13 μ m BCD technology is used to tape out the DC–DC converter of the improved voltage mode COT. The input voltage is 3.7–5.5 V and the output voltage is 3.3 V. The chip test mainly includes heavy-load condition in CCM operation, light-load condition in DCM operation, and load transient response. The test results show that the chip can remain stable under heavy-load and light-load conditions. The overshoot and undershoot in transient response can be quickly restored to steady state during the recovery process. Finally, compared with chips of the same type, it shows that the DC–DC chip for portable electronic equipment designed in this paper adopts an internal compensation structure, which has good stability, simple design, small main chip area, simple peripheral equipment, and good application value. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive multi-mode PWM control PSR flyback converter is proposed. In constant voltage (CV) mode, the converter adopts primary-side regulate (PSR) scheme to detect load information through the auxiliary winding, which reflects the load information on the voltage of V C O M P . The converter adjusts the switching frequency according to the voltage of V C O M P under different load conditions, realizing adaptive multi-mode PWM control to significantly improve light- load efficiency and thus the overall average efficiency. Besides, it does not give compromise to other system performance, such as audible noise, standby power consumption, and regulation. To verify the feasibility and performance of the proposed circuit, the converter has been designed and fabricated in HHGRACE_0.35 μ m BCD process and verified in a 5V/1A circuit prototype. The experimental results show that 25% load power efficiency of the proposed converter is 78.1%, which is improved by up to 3.4% compared to the conventional converter. [ABSTRACT FROM AUTHOR]

With the development of electric vehicles, the demand for the high-voltage low-current DC-DC chips used in vehicle on-board equipment continues to grow. To improve the efficiency of the switching power supply, an asynchronous buck high-voltage DC-DC converter with adaptive variable frequency modulation (AVFM) technology is designed in this paper. This work focuses on the efficiency optimization of the buck converter, and the relationship between power consumption and operating frequency under different loads. The optimal frequency range is selected during light and heavy loads, and adaptive transition of the frequency is realized during a medium load. Using a threshold voltage (Vth_cs) circuit with an adjustable current inside the chip, the on-time of the switch is changed to realize frequency conversion. The whole chip design is based on 0.35 μm BCD process, in which the integrated LDMOS can withstand 200 V. System simulations are completed in Cadence. The results show that when the input voltage is 30–60 V and the output specification is 5 V/0.5 A, the system realizes adaptive frequency conversion in the entire load range, and the efficiency reaches 88.9%. The actual performance of the chip meets the design requirements and has good EMI characteristics. [ABSTRACT FROM AUTHOR]

A primary-side regulation (PSR) constant current (CC) output and constant voltage (CV) output AC–DC converter is proposed and an adaptive high-precision closed-loop constant current control scheme is put forward in this paper. In the CC mode, the converter adopts the closed-loop control strategy to realize that the switching period adaptively converges to twice the demagnetization time, which realizes the CC output. In addition, exactly detecting the demagnetization time is a prerequisite for obtaining a high-precision output current. Therefore, a demagnetization time detection circuit is designed to provide accurate and reliable demagnetization information. The control IC was fabricated with the Nuvoton 0.5um BCD process, and a 5 V/2 A prototype circuit was implemented to verify its performance. Experimental results show that the CC deviation is within ± 1.4%, which is lower than the target value of ± 2.0%. Under different loads and AC inputs, the conversion efficiency in the CC mode varies between 76.3% and 80.7%. [ABSTRACT FROM AUTHOR]