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The project represents a report that introduces a data infrastructure that a) integrates data from multiple sources, b) enables various access permissions to differentstakeholders, c) provides model building and algorithm development within the data lake, and d) allows for the implementation of real-time analysis outputs including adaptive feedback and dashboards for both learners and teachers. This technical environment is foundation to the utilisation of artificial intelligence in knowledge processes and to establish advanced applications such as personal knowledge graphs and contextual learning supports that are indicative of true personalised learning and sensemaking, simultaneously advancing research and practice of teaching and learning.

Coarse-grained reconfigurable arrays (CGRAs) are programmable hardware platforms that can be used to realize application-specific accelerators for higher performance and energy efficiency. A CGRA is a 2D array of configurable logic blocks & interconnect, where the logic blocks are typically large & ALU-like, and the interconnect is word-wide. CGRA-ME is a software framework that enables the modelling and exploration of CGRA architectures, as well as research on CGRA CAD algorithms. With CGRA-ME, an architect can specify a CGRA architecture at a high level of abstraction. A set of applications can be mapped onto the architecture to assess the mappability, power, performance and cost. CGRA-ME also allows one to generate synthesizable Verilog RTL for the modelled CGRA, permitting its implementation as an ASIC or FPGA overlay. In this paper, we describe the CGRA-ME framework [5] and overview its capabilities and current limitations. We discuss ongoing and prior research conducted with the framework, as well as outline future plans. We believe CGRA-ME will be a valuable contribution to the community, enabling new research on CGRA CAD & architectures.

This companion paper supports the experimental replication of paper "Outfit Compatibility Prediction and Diagnosis with Multi-Layered Comparison Network", which is presented at ACM Multimedia 2019. We provide the software package for replicating the implementation of Multi-Layered Comparison Network (MCN), as well as the Polyvore-T dataset and baseline methods compared in the original paper. This paper contains the guides to reproduce the experiment results including outfit compatibility prediction, outfit diagnosis and automatic outfit revision.

Network-On-Chip design has been an active area of academic research for two decades, but many proposed ideas have not been adopted in real chips because they have complex behavior or create significant risks in chip implementation. For this reason, many existing chips just employ fast, replicated vanilla dimension-ordered mesh NoCs. However, these networks do not come close to utilizing the full available VLSI wiring capabilities, and propagate packets at speeds that are significantly below the raw speed of wires.The ideal network would not require any custom circuits, and would decompose easily into a hierarchical CAD flow consisting of a top-level design instantiating a mesh of identical hardened tiles with short-wire neighbor connections.At the same time, this ideal network would easily scale to efficiently utilize the majority of the available chip wiring resources, and would offer a mechanism for scaling this wire usage up or down based on available bandwidth. Packets would spend a significant fraction of their time in wire delay rather than router delay. Finally, the NoC would be simple to understand.This paper proposes Ruche Networks, which fulfill these requirements. They are based on simple 2-D mesh networks but amplify the NoC bandwidth and reduce NoC diameter of tiled architectures by adding long-range physical channels from each tile to other tiles on the same row or column. The more distant the connections, the greater the bandwidth of the network and the lower the diameter. The distance is typically increased until all of the physical VLSI wiring bandwidth have been absorbed.We explain the rational for this "ruching" and provide a simple methodology for designing and implementing these networks using a standard cell VLSI CAD flow.In this paper, we show the steps involved in ruching the HammerBlade Manycore’s mesh networks; these steps can easily apply to other designs.

Deep neural networks (DNNs) have been successfully applied to a great variety of applications, ranging from small IoT devices to large scale services in a data center. In order to improve the efficiency of processing these DNN models, dedicated hardware accelerators are required for all these scenarios. Theoretically, there exists an optimized acceleration architecture for each application. However, considering the cost of chip design and corresponding tool-chain development, researchers need to trade off between efficiency and generality. In this work, we demonstrate that it is practical to use a unified architecture, called Ascend, to support those applications, ranging from IoT devices to data-center services. We provide a lot of design details to explain that the success of Ascend relies on contributions from different levels. First, heterogeneous computing units are employed to support various DNN models. And the datapath is adapted according to the requirement of computing and data access. Second, when scaling the Ascend architecture from a single core to a cluster containing thousands of cores, it involves design efforts, such as memory hierarchy and system level integration. Third, a multi-tier compiler, which provides flexible choices for developers, is the last critical piece. Experimental results show that using accelerators based on the Ascend architecture can achieve comparable or even better performance in different applications. In addition, various chips based on the Ascend architecture have been successfully commercialized. More than 100 million chips have been used in real products.

This "success story" panel illustrates how next generation video applications are enabled on PCs today using consumer integrated and discrete GPUs launched in 2020. Intel's XeLP graphics technology with dedicated media hardware powers the integrated graphics in Intel's latest client processor, Tiger Lake, and Intel's first entry-level mainstream discrete graphics card, DG1. XeLP graphics in Tiger Lake and DG1 has democratized access to high performance implementations of the latest emerging video codec standards. Three topics will be covered: (i) 8K HEVC/AV1 Playback with Content Adaptive Power Optimization; (ii) Ludicrous Speed HEVC Encoding with Integrated + Discrete GPU; and (iii) MPEG Immersive Video (MIV) Playback on DG1.

Deep Neural Networks (DNNs) are the algorithm of choice for image processing applications. DNNs present highly parallel workloads that lead to the emergence of custom hardware accelerators. Deep Learning (DL) models specialized in different tasks require a programmable custom hardware and a compiler/mapper to efficiently translate different DNNs into an efficient dataflow in the accelerator. The goal of this paper is to present a compiler for running DNNs on Snowflake, which is a programmable hardware accelerator that targets DNNs. The compiler correctly generates instructions for various DL models: AlexNet, VGG, ResNet and LightCNN9. Snowflake, with a varying number of processing units, was implemented on FPGA to measure the compiler and Snowflake performance properties upon scaling up. The system achieves 70 frames/s and 4.5 GB/s of off-chip memory bandwidth for AlexNet without linear layers on Xilinx’s Zynq-SoC XC7Z045 FPGA.

This paper will describe high performance interface building blocks, compare their networking features and show how they may be used in small and large systems especially as they apply to SpaceVPX modules. Emphasis will be placed on their SpaceWire and other networking capabilities.1

Background Digitally enabled rehabilitation may lead to better outcomes but has not been tested in large pragmatic trials. We aimed to evaluate a tailored prescription of affordable digital devices in addition to usual care for people with mobility limitations admitted to aged care and neurological rehabilitation. Methods and findings We conducted a pragmatic, outcome-assessor-blinded, parallel-group randomised trial in 3 Australian hospitals in Sydney and Adelaide recruiting adults 18 to 101 years old with mobility limitations undertaking aged care and neurological inpatient rehabilitation. Both the intervention and control groups received usual multidisciplinary inpatient and post-hospital rehabilitation care as determined by the treating rehabilitation clinicians. In addition to usual care, the intervention group used devices to target mobility and physical activity problems, individually prescribed by a physiotherapist according to an intervention protocol, including virtual reality video games, activity monitors, and handheld computer devices for 6 months in hospital and at home. Co-primary outcomes were mobility (performance-based Short Physical Performance Battery [SPPB]; continuous version; range 0 to 3; higher score indicates better mobility) and upright time as a proxy measure of physical activity (proportion of the day upright measured with activPAL) at 6 months. The dataset was analysed using intention-to-treat principles. The trial was prospectively registered with the Australian New Zealand Clinical Trials Registry (ACTRN12614000936628). Between 22 September 2014 and 10 November 2016, 300 patients (mean age 74 years, SD 14; 50% female; 54% neurological condition causing activity limitation) were randomly assigned to intervention (n = 149) or control (n = 151) using a secure online database (REDCap) to achieve allocation concealment. Six-month assessments were completed by 258 participants (129 intervention, 129 control). Intervention participants received on average 12 (SD 11) supervised inpatient sessions using 4 (SD 1) different devices and 15 (SD 5) physiotherapy contacts supporting device use after hospital discharge. Changes in mobility scores were higher in the intervention group compared to the control group from baseline (SPPB [continuous, 0–3] mean [SD]: intervention group, 1.5 [0.7]; control group, 1.5 [0.8]) to 6 months (SPPB [continuous, 0–3] mean [SD]: intervention group, 2.3 [0.6]; control group, 2.1 [0.8]; mean between-group difference 0.2 points, 95% CI 0.1 to 0.3; p = 0.006). However, there was no evidence of a difference between groups for upright time at 6 months (mean [SD] proportion of the day spent upright at 6 months: intervention group, 18.2 [9.8]; control group, 18.4 [10.2]; mean between-group difference −0.2, 95% CI −2.7 to 2.3; p = 0.87). Scores were higher in the intervention group compared to the control group across most secondary mobility outcomes, but there was no evidence of a difference between groups for most other secondary outcomes including self-reported balance confidence and quality of life. No adverse events were reported in the intervention group. Thirteen participants died while in the trial (intervention group: 9; control group: 4) due to unrelated causes, and there was no evidence of a difference between groups in fall rates (unadjusted incidence rate ratio 1.19, 95% CI 0.78 to 1.83; p = 0.43). Study limitations include 15%–19% loss to follow-up at 6 months on the co-primary outcomes, as anticipated; the number of secondary outcome measures in our trial, which may increase the risk of a type I error; and potential low statistical power to demonstrate significant between-group differences on important secondary patient-reported outcomes. Conclusions In this study, we observed improved mobility in people with a wide range of health conditions making use of digitally enabled rehabilitation, whereas time spent upright was not impacted. Trial registration The trial was prospectively registered with the Australian New Zealand Clinical Trials Register; ACTRN12614000936628, In a randomised controlled trial, Leanne Hassett and colleagues investigate the impact of digitally-enabled aged care and neurological rehabilitation on activity and mobility outcomes in Australia., Author summary Why was this study done? A higher dose of therapy in physical rehabilitation is associated with better outcomes; however, current rehabilitation models deliver low therapy doses. Use of digital devices such as virtual reality video games, activity monitors, and handheld computer devices can be enjoyable, provide feedback on performance, and may enable a greater dose of task-specific therapy to improve outcomes. Current evidence is yet to confidently confirm the effects of rehabilitation using digital devices in addition to usual rehabilitation care on mobility tasks such as walking and other important outcomes such as quality of life. What did the researchers do and find? In a pragmatic, outcome-assessor-blinded randomised controlled trial, 300 people with walking difficulties (age 72 ± 16 years, 50% female) received usual multidisciplinary inpatient and post-hospital aged care and neurological rehabilitation alone, or in addition used a range of affordable devices such as virtual reality video games, activity monitors, and handheld devices to target mobility and physical activity, as individually prescribed by a physiotherapist for 6 months. On average participants in the intervention group used 4 ± 1 devices in the inpatient setting and 2 ± 1 devices in the post-hospital setting. This approach was feasible and enjoyed, and demonstrated it could be provided across care settings including the post-hospital setting with mostly remote support. Clinically important improvement was seen in mobility at 3 weeks and 6 months after baseline, but this was not accompanied by greater time spent upright. No adverse events were reported by participants whilst undertaking rehabilitation using digital devices, and there was no difference in the rate of falls between groups. What do these findings mean? Digitally enabled rehabilitation using a range of devices prescribed by a physiotherapist to target a range of mobility limitations across care settings for adults with mixed health conditions can improve mobility but not time spent upright. These results need to be interpreted in light of study limitations including a 15%–19% loss to follow-up at 6 months on the co-primary outcomes. Future models of rehabilitation should investigate incorporating digital devices to enhance inpatient and post-hospital rehabilitation, but prescription should ensure quality and quantity of practice.

This survey reviews several approaches of HPDM from many research groups world wide. Modern computer hardware supports the development of high-performance applications for data analysis on many different levels. The focus is on modern multi-core processors built into today's commodity computers, which are typically found at university institutes both as small server and workstation computers. So they are deliberately not high-performance computers. Modern multi-core processors consist of several (2 to over 100) computer cores, which work independently of each other according to the principle of "multiple instruction multiple data'' (MIMD). They have a common main memory (shared memory). Each of these computer cores has several (2-16) arithmetic-logic units, which can simultaneously carry out the same arithmetic operation on several data in a vector-like manner (single instruction multiple data, SIMD). HPDM algorithms must use both types of parallelism (SIMD and MIMD), with access to the main memory (centralized component) being the main barrier to increased efficiency.

Despite tremendous advancement of digital IC design automation tools over the last few decades, analog IC layout is still heavily manual which is very tedious and error-prone. This paper will first review the history, challenges, and current status of analog IC layout automation. Then, we will present MAGICAL, a human-intelligence inspired, fully-automated analog IC layout system currently being developed under the DARPA IDEA program. It starts from an unannotated netlist, performs automatic layout constraint extraction and device generation, then performs placement and post-placement optimization, followed by routing to obtain the final GDSII layout. Various analytical, heuristic, and machine learning algorithms will be discussed. MAGICAL has obtained promising preliminary results. We will conclude the paper with further discussions on challenges and future directions for fully-automated analog IC layout.

Wavelength-routed optical network-on-chip (WRONoC) design consists of topological and physical synthesis. It covers many interacting design aspects such as wavelength assignment, message routing, network construction, component placement, and waveguide routing. Due to the high complexity of the design problem, current manual design usually trades optimality for scalability and feasibility, which results in performance degradation and waste of resources. In this paper, we will present an overview of the existing design automation approaches that have demonstrated their effectiveness in customizing and optimizing application-specific WRONoC designs, and of the potential design automation directions to address a wider range of design challenges. We will also discuss the advantages of comprehensive optimization considering multiple design aspects simultaneously, and the possible barriers that need to be removed to achieve this goal.

This paper reviews the results of recent researches aimed to extend the standard-cell based digital design flow to analog building blocks, so that to enhance scalability, reconfigurability and portability across technology nodes and to reduce design effort, time-to-market and costs. In this framework, the application of the proposed fully digital design approach to a wake up oscillator and to a Digital-to-Analog Converter, which are two building blocks widely employed in IoT sensor nodes, is illustrated in detail.

Neuromorphic chips are electronic hardware mimicking neurons in human brain in an electronic structure. These ASICs (Application Specific Integrated Circuits) provide artificial neural networks with computational power comparatively higher than most neural networks generated by software algorithms. 'CM1K' is an electronic chip in this family of products. It has a parallel neural network of 1024 neurons. These neurons provide K-Nearest Neighbor (KNN) data classification. The chip requires to be embedded in an electronic system to access all its capabilities. This paper deliver a novel hardware system embedding CM1K neuromorphic chip. The system was implemented in image and video frame analysis for evaluation. The results prove that the system could benefit various applications including security, asset management, home appliances, mail sorting and manufacturing. Since the embedded system provide opportunity to integrate AI in to simple electronics, it helps on extending AI applications.

The fifth generation of mobile communications (5G) is expected to dramatically improve performance compared to preceding standards by offering very high bandwidths and low latencies. To provide this performance, heavy processing is required and must meet strong timing constraints. Reconfigurable computing, managing processing in software and exploiting reconfigurable hardware acceleration, is an innovative approach that should be considered for 5G for its capacity to combine high throughput and high flexibility. This paper presents a case study for Orthogonal Frequency Division Multiplexing (OFDM) computation reconfigurable offloading onto an Field Programmable Gate Array (FPGA). The implementation is based on Open Computing Language (OpenCL) that represents a versatile solution, as this language can be compiled for several architectures, provided that a Host+Accelerator structure is used. The objective of our study is to demonstrate that, by means of hardware offloading, the 5G architecture resources can reach high computational load, avoiding processing stalls and latency increase. Results show that around 15% of the software processing can be freed through hardware acceleration and reallocated to support other tasks.

The increasing complexity of modern Integrated Circuits (ICs) leads to systems composed of various different Intellectual Property (IPs) blocks, known as System-on-Chip (SoC). Such complexity requires strong expertise from engineers, that rely on expansive commercial EDA tools. To overcome such a limitation, an automated open-source logic synthesis flow is required. In this context, this work proposes LSOracle: a novel automated mixed logic synthesis framework. LSOracle is the first to exploit state-of-the-art And-Inverter Graph (AIG) and Majority-Inverter Graph (MIG) logic optimizers and relies on a Deep Neural Network (DNN) to automatically decide which optimizer should handle different portions of the circuit. To do so, LSOracle applies $k-way$ partitioning to split a DAG into multiple partitions and uses a to chose the best-fit optimizer. Post-tech mapping ASIC results, targeting the 7nm ASAP standard cell library, for a set of mixed-logic circuits, show an average improvement in area-delay product of 6.87% (up to 10.26%) and 2.70% (up to 6.27%) when compared to AIG and MIG, respectively. In addition, we show that for the considered circuits, LSOracle achieves an area close to AIGs (which delivered smaller circuits) with a similar performance of MIGs, which delivered faster circuits.

The International Symposium on Computer Architecture (ISCA) recognizes every year the most influential paper published in this conference 15 years earlier, based on its impact on research, development, products or ideas. This award is sponsored by the IEEEComputer Society Technical Committee on Computer Architecture (IEEE-CS TCCA) and the ACM Special Interest Group on Computer Architecture (ACM SIGARCH). In this year’s edition, the candidate papers were those papers published in ISCA 2003 proceedings.The selection process was chaired by Antonio González. Candidate papers for the award were selected by the current year’s ISCA Pro-gram Committee. The final award selection was made by the Award Chair (Antonio González), the IEEE-CS TCCA Chair (Lieven Eeckhout) and the ACM SIGARCH Chair (Sarita Adve). The award includes an honorarium for the authors and a certificate.The 2018 award was presented to “Temperature-Aware Microarchitecture” by Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan and DavidTarjan.

In this paper, we present full-chip designs and their power, performance, and area (PPA) metrics using the ASAP7 process design kit (PDK) and library. Reliable cell library is a key element in evaluating new technological options such as monolithic 3D (M3D) ICs. Given an RTL, we conduct synthesis and place/route to obtain commercial-quality 2D and M3D IC designs and compare PPA. The ASAP7 library is highly useful to build high-quality designs that accurately reflect 7nm technology node. In addition, the full front-end and back-end access provided in ASAP7 allows us to see the impact of various device and interconnect parameters at the full-chip level for both 2D and monolithic 3D ICs. This work demonstrates the critical role of an academic PDK and library in enabling high-quality research in disruptive technologies such as M3D integration.

This work discusses the ASAP7 predictive process design kit (PDK) and associated standard cell library. The necessity for multi-patterning (MP) techniques at advanced nodes results in the standard cell and SRAM architecture becoming entangled with design rules, mandating design-technology co-optimization (DTCO). This paper discusses the DTCO process involving standard cell physical design. An assumption of extreme ultraviolet (EUV) lithography availability in the PDK allows bi-directional M1 geometries that are difficult with MP. Routing and power distribution schemes for self-aligned quadruple patterning (SAQP) friendly, high density standard cell based blocks are shown. Restrictive design rules are required and supported by the automated place and route (APR) setup. Supporting sub-20 nm dimensions with academic tool licenses is described. The APR (QRC techfile) extraction shows high correlation with the Calibre extraction deck. Finally, use of the PDK for academic coursework and research is discussed.

Standard cell libraries are the foundation for the entire back-end design and optimization flow in modern application-specific integrated circuit designs. At 7nm technology node and beyond, standard cell library design and optimization is becoming increasingly difficult due to extremely complex design constraints, as described in the ASAP7 process design kit (PDK). Notable complexities include discrete transistor sizing due to FinFETs, complicated design rules from lithography and restrictive layout space from modern standard cell architectures. The design methodology presented in this paper enables efficient and high-quality standard cell library design and optimization with the ASAP7 PDK. The key techniques include exhaustive transistor sizing for cell timing optimization, transistor placement with generalized Euler paths and back-end design prototyping for library-level explorations.

This paper investigates the multi-broker based network control and management paradigm for realizing scalable and cost-effective service provisioning in multi-domain software-defined optical networks. Experimental results verify the feasibility of the proposal and demonstrate ∼ 7.6× blocking reduction comparing with the conventional single-broker based solution.

Domain-Specific Languages (DSLs) provide a high-level and domain-specific abstraction to describe algorithms within a certain domain concisely. Since a DSL separates the algorithm description from the actual target implementation, it offers a high flexibility among heterogeneous hardware targets, such as CPUs and GPUs. With the recent uprise of promising High-Level Synthesis (HLS) tools, like Vivado HLS and Altera OpenCL, FPGAs are becoming another attractive target architecture. Particularly in the domain of image processing, applications often come with stringent requirements regarding performance, energy efficiency, and power, for which FPGA have been proven to be among the most suitable architectures. In this work, we present the Hipacc framework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs. Our approach includes FPGA-specific memory architectures for handling point and local operators, as well as several high-level transformations. We evaluate our approach by comparing the resulting hardware accelerators to GPU implementations, generated from exactly the same DSL source code.

Spiking Neural Network based brain-inspired computing paradigms are becoming increasingly popular tools for various cognitive tasks. The sparse event-driven processing capability enabled by such networks can be potentially appealing for implementation of low-power neural computing platforms. However, the parallel and memory-intensive computations involved in such algorithms is in complete contrast to the sequential fetch, decode, execute cycles of conventional von-Neumann processors. Recent proposals have investigated the design of spintronic “in-memory” crossbar based computing architectures driving “spin neurons” that can potentially alleviate the memory-access bottleneck of CMOS based systems and simultaneously offer the prospect of low-power inner product computations. In this article, we perform a rigorous system-level simulation study of such All-Spin Spiking Neural Networks on a benchmark suite of 6 recognition problems ranging in network complexity from 10k–7.4M synapses and 195–9.2k neurons. System level simulations indicate that the proposed spintronic architecture can potentially achieve ∼1292× energy efficiency and ∼ 235× speedup on average over the benchmark suite in comparison to an optimized CMOS implementation at 45nm technology node.

The research work explains a cost-effective, highperformance computing platform for the parallel implementation of the FDTD algorithm on PC clusters using the message-passing interface (MPI) library, which is a local area network system consisting of multiple interconnected personal computers (PCs), and is already widely employed for parallel computing.

This article discusses the 2017 ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award, which was given to the 2002 ISCA paper, “Drowsy Caches: Simple Techniques for Reducing Leakage Power.”

This column discusses two awards given in 2014: the International Symposium on Computer Architecture Influential Paper Award, which was given to the authors of the paper "PipeRench: A Coprocessor for Streaming Multimedia Acceleration," and the Maurice Wilkes Award, which was given to Ravi Rajwar.

Hybrid systems combine Large-Area Electronics (LAE) with high-performance technologies (e.g., silicon CMOS) [1]. With architectural concepts for hybrid systems broadening to match the range of emerging applications, this paper examines modular approaches for multi-sheet, multi-technology integration. It identifies the interfaces required as a critical backbone. For interfaces associated with various system functionalities (sensing, processing, powering), specific approaches are surveyed and analyzed, taking from insights derived from several previous experimental demonstrations of complete hybrid systems.

Latency, Area, and Power are three important metrics that a VLSI designer wants to optimize. However, often one of these may have to be optimized at the cost of another or the other two. Depending on the application scenario, choice of the metric to optimize is made. In this paper, we consider hardware implementations of a number of cryptographic primitives and present a number of optimizations. We consider three areas of cryptoengineering. They are building physical unclonable functions (PUFs), implementing encryption/decryption algorithms, and side channel proof crypto implementations. The techniques we employ range from area optimization through customized multiplexer design, fusing multiple operations into a single hardware element, folding and unrolling of iterative algorithms, creating reconfigurable implementations to achieve multiple operations with the same set of hardware elements, to techniques of obfuscation to defeat fault injection based attacks on the crypto implementation. All the proposed and existing designs are implemented with 45 nm CMOS library.

Conference of 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016 ; Conference Date: 17 July 2016 Through 21 July 2016; Conference Code:126004; International audience; The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous micro server computing resources, being able to be tailored to meet requirements from various application domains, including the Internet of Things. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated; advanced management strategies and system efficiency enhancements (SEE); well-defined interfaces to surrounding software data centre ecosystem.

The explosion of big data applications imposes severe challenges of data processing speed and scalability on traditional computer systems. However, the performance of the von Neumann machine is greatly hindered by the increasing performance gap between CPU and memory, motivating the active research on new or alternative computing architectures. As one important instance, neuromorphic computing systems inspired by the working mechanism of human brains have gained considerable attention. In this work, we propose a heterogeneous computing system with neuromorphic computing accelerators (NCAs) that are built with emerging memristor technology. In the proposed system, NCA is designed to speed up the artificial neural network (ANN) executions in many high-performance applications by leveraging the extremely efficient mixed-signal computation capability of nanoscale memristor-based crossbar (MBC) arrays. The hierarchical MBC arrays of the NCA can be flexibly configured to different ANN topologies through the help of an analog Network-on-Chip (A-NoC). A general approach which translates the target codes within a program to the corresponding NCA instructions is also developed to facilitate the utilization of the NCA. Our simulation results show that compared to the baseline general purpose processor, the proposed heterogeneous system can achieve on average 18.2x performance speedup and 20.1x energy reduction over nine representative applications while constraining the computation accuracy degradation within an acceptable range.