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An ultra‐low quiescent current tri‐mode DC–DC boost converter is proposed in this paper, which can efficiently handle loads from 1 μA to 300 mA, providing 5‐V output from 3 to 4.2‐V input. Hysteresis current mode control is adopted to realize seamless mode switching between continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In order to deal with the light load situation, this paper proposes a quasi burst mode (QBM). In this mode, most of the modules are turned off and only the QBM controller, low‐power current bias and sample and hold circuit are retained, which significantly reduces the static current of the converter, and thus improves the light load efficiency. Meanwhile, the average current of error amplifier and comparator are reduced significantly by dynamic biasing. Finally, the efficiency of the converter is greatly improved and kept at a reasonable output ripple. The proposed converter is implemented in a 0.13‐μm BCD process design and manufacturing. The test results show that the quiescent current of the converter is only 780 nA, which can achieve a peak efficiency of 95.6%, and ensure that the efficiency is maintained above 80% in the load range of 10 μA to 300 mA. [ABSTRACT FROM AUTHOR]

In order to achieve high efficiency in a wider load range, a PWM/PFM/Power-Saved mode dc–dc buck converter is proposed. The mode switching technique is based on an accurate power loss model consisting of critical components/parameters: The size of the power transistor and the ON/OFF status of power-hungry subcircuits. The circuit of mode switching technique is achieved by the reference, pulse skipped modulation (PSM) comparator and feedback resistors, and its own consumption of quiescent current is extremely low. At ultra-light load, by detecting the ZCD duration and the ripple of the output, the system can switch to the Power-Saved-Mode. The proposed buck converter was implemented by using a 0.18 μ m CMOS process. It achieves a peak efficiency of 97% and > 90% efficiency from 100 μ A to 600 mA. A 360 nA quiescent current is achieved. With a low output ripple of less than 60 mV, the input voltage range and regulated output voltage are 3.6–5 V and 1.2–3.3 V, respectively. [ABSTRACT FROM AUTHOR]

In this paper, an improved voltage-mode constant on-time (COT) control DC–DC buck converter is designed, which makes the DC–DC buck converter have good stability. Firstly, an improved compensation scheme is introduced through the analysis and derivation of the traditional voltage-mode COT controlled buck converter model. Then, according to the application requirements of the design, Simplis software modeling is used to verify the correctness of the theoretical analysis. The 0.13 μ m BCD technology is used to tape out the DC–DC converter of the improved voltage mode COT. The input voltage is 3.7–5.5 V and the output voltage is 3.3 V. The chip test mainly includes heavy-load condition in CCM operation, light-load condition in DCM operation, and load transient response. The test results show that the chip can remain stable under heavy-load and light-load conditions. The overshoot and undershoot in transient response can be quickly restored to steady state during the recovery process. Finally, compared with chips of the same type, it shows that the DC–DC chip for portable electronic equipment designed in this paper adopts an internal compensation structure, which has good stability, simple design, small main chip area, simple peripheral equipment, and good application value. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive multi-mode PWM control PSR flyback converter is proposed. In constant voltage (CV) mode, the converter adopts primary-side regulate (PSR) scheme to detect load information through the auxiliary winding, which reflects the load information on the voltage of V C O M P . The converter adjusts the switching frequency according to the voltage of V C O M P under different load conditions, realizing adaptive multi-mode PWM control to significantly improve light- load efficiency and thus the overall average efficiency. Besides, it does not give compromise to other system performance, such as audible noise, standby power consumption, and regulation. To verify the feasibility and performance of the proposed circuit, the converter has been designed and fabricated in HHGRACE_0.35 μ m BCD process and verified in a 5V/1A circuit prototype. The experimental results show that 25% load power efficiency of the proposed converter is 78.1%, which is improved by up to 3.4% compared to the conventional converter. [ABSTRACT FROM AUTHOR]

A small‐signal model is established for the basic constant voltage (CV) flyback converter firstly. Then the phase margin and the bandwidth, which can reflect the system stability and rapidity, are deduced through transfer function. The parameters affecting the stability of the system can be obtained by the model's derivation to confirm the appropriate external capacitance value. To improve the precision of CV, the compensation of cable is implemented through the module of irrigation current, pulling down the output voltage under any load conditions to the value of it with the maximal load. The prototype for the proposed CV converter has been fabricated in an MXIC 0.8 μm L80A1 process. The minimal static power consumption measured by a test is only 40 mW. In the CV mode, the precision of the output voltage can reach the level of ±1.5%. Therefore, the proposed control chip has a promising application in low power CV AC–DC flyback converter. [ABSTRACT FROM AUTHOR]

This paper presents electrolytic capacitorless AC/DC LED driver. It adopts Boost–Buck topology, through modulation of the conduction time T on and the change of input current reference, to reduce the instantaneous input and output power difference, so a smaller film capacitor can be used instead of the electrolytic capacitor. Therefore, LED driver power life has been effectively improved. The Buck converter operates in the inductor current discontinuous conduction mode to achieve constant output current by controlling the peak current. The control IC is fabricated in TSMC 0.35- μ m 5-V/650-V CMOS/LDMOS process, and verified in a 72-V/150-mA circuit prototype. The test results show that when the range of input voltage is 175–264 Vac, the efficiency of the system is 83%, the voltage linear regulation is ± 1 %, the load regulation is ± 0. 5 %, and the electrolytic capacitor is replaced by 470-nF CBB capacitor under the condition that the power factor is above 0.7. Therefore, the design of the control chip in the LED driver has a very good application prospect. [ABSTRACT FROM AUTHOR]

In this paper, based on the combination scheme of dual-sampling and adaptive predictive PID control, a digital controller for improving the transient performance of Buck DC–DC converters is designed. Due to the inherent loop delay in analog-to-digital (A/D) conversion, the calculation process of the digital controller and digital pulse width modulator (DPWM) of conventional digitally-controlled Buck DC–DC converters limits the system bandwidth and this makes the transient response lower. The designed digital controller can reduce the delay time in analog-to-digital converter (ADC), the digital controller and DPWM of digitally-controlled Buck DC–DC converters. Adaptive predictive control is used to eliminate the delay time of ADC and the digital controller, while dual-sampling scheme is used to reduce the delay time of DPWM in this paper. These are two new control schemes, and they show better performance in improving the transient response than other existing control schemes. Both simulation and experimental results demonstrate that the designed digital controller based on dual-sampling and adaptive predictive PID control is effective in improving the transient performance of Buck DC–DC converters. During experimental verification, for a load step between 0.5 A and 1.0 A, the fastest transient recovery time and the overshoot voltage are found to be 102 μ s and 120 mV, respectively. Compared with the conventional digital PID controller, the transient recovery time and the overshoot voltage of the digital controller designed in this paper are decreased by 40.0% and 27.3%, respectively. [ABSTRACT FROM AUTHOR]

With the development of portable electronic products, the requirement for chargers is also getting higher. In this paper, a high-accuracy constant output current/constant output voltage (CC/CV) ac–dc flyback converter is proposed and a novel cable compensation method without external capacitor is put forward. The converter adopts primary-side regulation (PSR) scheme, detecting the output voltage through the auxiliary winding, and adjusting switching frequency to achieve output voltage constant in CV mode. Compared to conventional cable compensation module, the proposed circuit applies a method of pre-filtering, averaging, and re-filtering, to obtain the compensation voltage. This method eliminates the need of external capacitor, reducing cost and increasing reliability of the converter. In CC mode, the switching period is adjusted to be fixed multiple of the demagnetization time, thereby realizing the constant current output. The control chip was implemented in NEC 1 μm HVCMOS process, and a 5-V/1-A prototype has been built to verify its feasibility. Experimental results show that the deviations of output voltage and current are within ±0.9% and ±3% under different inputs and loads, while maximum conversion efficiency can reach a level of 78.2%. [ABSTRACT FROM AUTHOR]

A constant voltage AC-DC converter based on the digital assistant technology is proposed in this paper, which has the advantage of high output precision. In this paper, a novel digital exponential wave generator is adopted in Constant Voltage (CV) mode to replace the normal triangle waveform to obtain a wider range of switching frequency, increasing the accuracy of output voltage under light load. The control chip is implemented based on NEC 1m 5V/40V HVCMOS process, and a 5V/1.2A prototype has been built to verify the proposed control method. In PFM mode the deviation of output voltage is within % and the load regulation is %. Meanwhile, when the load jumps from light to heavy, the minimum output voltage could be maintained above 4.16V. [ABSTRACT FROM AUTHOR]

A primary‐side controlled high‐precision constant current AC–DC LED driver, based on source‐driving control scheme, is designed for low‐power LED‐lighting applications in this study. The ratio between demagnetisation time TDemag and switching period TS and the primary peak current are remained constant by the proposed control IC, obtaining constant current output. Meanwhile, an adaptive line voltage compensation circuit, integrated in the primary peak current controller, is proposed based on source‐driving control scheme. A compensation current proportional to line voltage is injected to the primary‐side current sampling pin CS, thus making the turn‐off bandgap reference of primary peak current under high‐line voltage lower than that under low‐line voltage. As a consequence, overshoot phenomena of primary peak current can be avoided, and the line regulation as well as the precision of output current can be improved. The proposed control IC has been fabricated in TSMC 0.35 μm 5 V/650 V CMOS/LDMOS process. Experimental results of a 5 W prototype show that the output current is kept stable at ∼250 mA, and the line regulation is within ±0.5% in a wide range of universal‐input ac voltage from 85 to 264 V, and that >80% efficiency is obtained under heavy LED loads. [ABSTRACT FROM AUTHOR]

This paper proposes a high-precision primary-side regulation constant voltage (CV) and constant current (CC) ac–dc converter. CV output is achieved by adjusting the switching frequency and primary peak voltage simultaneously, for better dynamic adjustment ability. In order to improve CV precision, a cable compensation module is adopted to inject current to pull-down resistor of auxiliary winding divider, compensating the cable voltage loss caused by the output cable resistance. On the other hand, CC output is acquired by maintaining the ratio of switching frequency and output voltage constant. The inductance compensation module regulates further to keep the product of demagnetization time and switching frequency fixed, equalizing the inconsistent output current result from the big tolerance of the transformer primary-side inductance in the same batch. Moreover, an improved demagnetization time detector is proposed, which is beneficial to raise CC precision. The control chip is implemented based on TSMC 0.35-μm 5-V/40-V BCD process, and a 12 V/1 A prototype has been built to prove the proposed control method. In CV mode, the deviation of the output voltage is within ±1.5%, while that of output current is within ±3% in CC mode. [ABSTRACT FROM AUTHOR]

A novel digital constant output current controller with demagnetization-time compensation for flyback converter is proposed in this paper. The secondary winding demagnetization time is sampled from the comparison module output signal by output voltage sampling state machine. The ratio between and switching period is kept constant by bidirectional counter module to achieve constant output current based on invariable primary-side peak-current. Meanwhile, demagnetization-time compensation is proposed in order to enhance load regulation ratio. The compensation acquired from a look-up table, is utilized to compensate the impacts caused by the delay from the process of sampling the signal of . The digital controller (DC) is implemented by hardware description language Verilog HDL. Experimental results of the proposed 2A constant current output flyback converter based on FPGA(EP2C8Q208C8N) indicate that the constant current precision is within 1% in a wide range of universal-input AC voltage from 110V to 240V and the voltage load range between 2V and 8V. [ABSTRACT FROM AUTHOR]

This paper presents a digitalized gyroscope system using $\Sigma \Delta $ modulation on ADC (Analog to Digital Converter) and DAC (Digital to Analog Converter) sections. Both discrete ADC and DAC chips are replaced with these \Sigma \Delta $ sections. The \Sigma \Delta $ ADC technology can convert signals between analog and digital domain using analog modulators on the printed circuit board circuit with different amplifiers and matched capacity couples and digital backend processing in field programmable gate array (FPGA). While the \Sigma \Delta $ ADC technology are easily realized in FPGA by signal processing algorithms the major sections of the digital system, such as auto gain control and phase-lock loop are also implemented in FPGA, which have provided the programmable flexibility of the whole system. The signal-to-noise ratio of power spectrum density (PSD) and stability in both \Sigma \Delta $ ADC and \Sigma \Delta $ DAC are analyzed, respectively. Considering the sections of the \Sigma \Delta , bandwidth of 75 Hz, and the bias instability of 2.94°/h. [ABSTRACT FROM PUBLISHER]