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Interest in creating and studying silicon-based InSb nanocrystals is due to the need for hybrid integrated circuits involving elements with different functional properties. Optical phonons localized in low-dimension crystals can affect both the optical and electrical properties of these crystals. The optical-phonon properties of InSb nanocrystals ion-beam synthesized in silicon and InSb nanocrystals formed in SiO2 layers by ion-beam synthesis and rf magnetron sputtering are compared. The properties of optical phonons in InSb nanocrystals are explained in terms of the effect of the structural properties of the surrounding matrix. [ABSTRACT FROM AUTHOR]

The main objective of this paper is to correctly define the hybrid equivalent circuits. These circuits allow the separation of the linear portions of electronic circuits from the nonlinear ones and in this way the polarization process of electronic devices becomes much more efficient. When linear and/or nonlinear analyzed circuits have a small number of nonlinear circuit elements, their analysis, synthesis, and simulation are performed more efficiently if the nonlinear part of circuit is separated from the linear one. A new modeling technique, called H ~ modeling, is introduced for multi-port networks. It is shown that H ~ models are more dynamic compared to equivalent Thevenin or Norton circuits and have the ability to describe port behavior more accurately. A special type of model H ~ is also introduced, called model H ~ nullified, or simply model H ~ and many properties of H modeling are investigated, including circuit energy management. It is shown that the H models are not limited to single-port networks, but also cover multiport. A major property of H modeling is the local polarization of transistors. It separates the nonlinear components from the linear portion of circuit for faster and more efficient polarization of circuit. Here a designer can take advantage of H-modeling and bias individual transistors (or in combinations) with no need to perform the normal circuit biasing. The proposed strategy separates linear and nonlinear portions of an analog circuit and takes more control of nonlinear portions. This separation of portions (components) of circuit is achieved by introducing a new port model that cancels the ports of nonlinear devices. In turn, this leads to a new technique for polarizing nonlinear components. This separation of portions (components) within the circuit is accomplished by introducing a new port modeling that nullifies the ports of nonlinear devices. [ABSTRACT FROM AUTHOR]

Summary: This paper presents the on‐chip evolution system of combinational logic circuits by a new hybrid algorithm known as improved genetic‐simulated annealing algorithm (IGASA). IGASA is based on the concept and principles of genetic algorithm (GA) and simulated annealing (SA). The main idea is to combine GA's global search ability with the advantage of SA's fast convergence to reach an optimal solution. In this paper, a new mutation operation and a repeated annealing (RA) process are introduced to overcome the premature convergence of the standard GA and the large number of searches in the later period. An elitist strategy to enhance convergence characteristic of the proposed algorithm is incorporated to better speed up the evolution process. In addition, the new algorithm is implemented in a new evolvable platform using Intel Cyclone V FPGA with an embedded ARM microprocessor. Comparison of the performance of the improved algorithm to the pure GASA algorithm and standard GA is presented on a number of case studies. The experiment results demonstrate that feasible circuits are always achieved by the IGASA algorithm unlike with other algorithms and the number of generations required is less. [ABSTRACT FROM AUTHOR]

Practical superconducting quantum interference devices (SQUIDs) have been developed into multiloop hybrid electric circuits with Josephson junctions and normal elements such as resistor, inductor and capacitor. To find a common circuit analysis and simulation method for different types of SQUID hybrid circuits consist of both superconducting and normal components, we introduce a mesh-current method, which can derive both the general system model and uniform circuit equations directly from the equivalent circuit. The mesh-current method is demonstrated in the simulation of a SQUID additional positive feedback circuit. The numerical simulation results are presented and verified with the measurements. Compared with the conventional nodal analysis method, the mesh-current method is excellent in dealing with the relations including external flux, self and mutual inductances in multiloop hybrid circuit analysis; its final circuit equations directly exhibit the physical theorems; its general system model reveals the quantum interference mechanism inside SQUID circuits, and is applicable for further dynamics studies. [ABSTRACT FROM AUTHOR]

Background: The use of extracorporeal circulation (ECC) for intraoperative cardiopulmonary support during lung transplantation has been increasing in the recent years. Our group previously described a novel hybrid extracorporeal membrane oxygenation (ECMO) circuit for use in lung transplantation. Technique: Our approach for intraoperative management of our novel hybrid ECMO circuit for lung transplantation is driven by two main goals: The first is to deliver management that ensures an appropriate balance between the native and ECMO cardiac outputs in order to provide a stable environment that promotes attenuation of ischemic‐reperfusion injury during implantation. The second is to provide a stable hemodynamic environment that results in an appropriate global perfusion guided by multiple monitors and an organ systems‐based approach during implantation. Comments: Our novel technique for intraoperative management of this circuit during lung transplantation is described. [ABSTRACT FROM AUTHOR]

The development of quantum electronic devices operating below a few Kelvin degrees is raising the demand for cryogenic complementary metal-oxide-semiconductor electronics (CMOS) to be used as in situ classical control/readout circuitry. Having a minimal spatial separation between quantum and classical hardware is necessary to limit the electrical wiring to room temperature and the associated heat load and parasitic capacitances. Here, we report prototypical demonstrations of hybrid circuits combining silicon quantum dot devices and a classical transimpedance amplifier, which is characterized and then used to measure the current through the quantum dots. The two devices are positioned next to each other at 4.2 K to assess the use of the cryogenic transimpedance amplifier with respect to a room-temperature transimpedance amplifier. A quantum device built on the same substrate as the transimpedance amplifier is characterized down to 10 mK. The transimpedance amplifier is based on commercial 28 nm fully depleted Silicon-on-insulator (FDSOI) CMOS. It consists of a two-stage Miller-compensated operational amplifier with a 10 MΩ polysilicon feedback resistor, yielding a gain of 1.1 × 10 7 V/A. We show that the transimpedance amplifier operates at 10 mK with only 1 μW of power consumption, low enough to prevent heating. It exhibits linear response up to ±40 nA and a measurement bandwidth of 2.6 kHz, which could be extended to about 200 kHz by design optimization. The realization of custom-made electronics in FDSOI technology for cryogenic operation at any temperature will improve measurement speed and quality inside cryostats with higher bandwidth, lower noise, and higher signal-to-noise ratio. [ABSTRACT FROM AUTHOR]

Extraction of the current commutation loop (CCL) inductance is necessary for the overvoltage analysis of power devices. In general, each transient process of a converter corresponds to a specific CCL. However, there is no such single CCL in the full-bridge module in hybrid dc circuit breakers during the turn-off transient. First, this article proposes a coupled inductance model of full-bridge modules. The model has less number of inductance compared to the traditional partial inductance model. Second, this article proposes the extraction method of inductances that can be easily obtained by both simulation and measurement. Moreover, the measured overvoltage waveforms of insulated gate bipolar translators (IGBTs) in the full-bridge module agree with the simulation results. Third, we propose an equivalent circuit of the series full-bridge modules in a 500 kV hybrid circuit breaker based on the proposed coupled inductance model. The mutual inductances among different modules are considered due to the compact structure of the series modules. The measured results show that the overvoltage of the IGBT in the series module could be well-predicted by the proposed equivalent circuit. [ABSTRACT FROM AUTHOR]

The coordination of resistive-type superconducting fault current limiters (R-SFCLs) and DC circuit breakers (DCCBs) have been investigated. However, the use of R-SFCLs with mechanical DCCBs (M-DCCBs) in hybrid transmission systems has not been studied. The objective of this paper is to investigate the parameter requirements of R-SFCLs and M-DCCBs for a detailed system protection strategy in a hybrid AC/DC system considering the influence of AC faults and three types of DC faults. When the AC fault is far from all MMCs, its impact on the DC system is weak. If the AC fault is close to one MMC, it will produce a strong transient response in the DC part. Therefore, a bypass switch in parallel with an R-SFCL is used to remove the R-SFCL from the system if it quenches during the AC fault. Then, the parameters of the protection devices are designed based on pole-to-pole DC fault. System restoration can be achieved within 200 ms after the fault. For pole-to-neutral and pole-to-ground faults, except for the R-SFCLs at the faulty pole, the R-SFCLs at the healthy pole will also quench, but the resistances are very low. The system may be restored within 250 ms after the DC fault. [ABSTRACT FROM AUTHOR]

A hybrid dc transformer (DCT) combining multiple series resonant converters (SRCs) and dual-active bridge (DAB) converters with input-series-output-parallel (ISOP) configuration is proposed in this article. The proposed DCT is suitable for connecting medium-voltage dc and low-voltage dc distribution networks, which combines SRCs as the majority modules for power transmission and DAB converters as the minority modules for terminal voltage regulation or power regulation. Benefiting from the hybrid circuit topology, the proposed DCT can achieve a higher efficiency than the ISOP DAB converters with a reduced complexity in the communication and control, while maintaining the controllability of the dc voltage/power. The operation principles of the proposed DCT are analyzed and key parameters design are presented. Then, a 1 MW, 10 kV/750 V hybrid DCT is simulated and a DCT prototype of 2 kW, 400/100 V is built to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

The all-optical magnetization reversal of magnetic layers, by picosecond optical pulses, is of particular interest as it shows the potential for energy-efficient and fast magnetic tunnel junction (MTJ) elements. This approach requires memory elements that are optically and electronically accessible, for optical writing and electronic read-out. In this paper, we propose the integration of indium tin oxide (ITO) as a transparent conducting electrode for magnetic tunnel junctions in integrated spintronic–photonic circuits. To provide light with sufficient energy to the MTJ free layer and allow electrical read-out of the MTJ state, we successfully integrated indium tin oxide as a top transparent electrode. The study shows that ITO film deposition by physical vapor deposition with conditions such as high source power and low O2 flow achieves smooth and conductive thin films. Increase in grain size was associated with low resistivity. Deposition of 150 nm ITO at 300 W, O2 flow of 1 sccm and 8.10−3 mbar vacuum pressure results in 4.8 × 10−4 Ω.cm resistivity and up to 80% transmittance at 800 nm wavelength. The patterning of ITO using CH4/H2 chemistry in a reactive ion etch process was investigated showing almost vertical sidewalls for diameters down to 50 nm. The ITO based process flow was compared to a standard magnetic tunnel junctions fabrication process flow based on Ta hard mask. Electrical measurements validate that the proposed process based on ITO results in properties equivalent to the standard process. We also show electrical results of magnetic tunnel junctions having all-optical switching top electrode fabricated with ITO for optical access. The developed ITO process flow shows very promising initial results and provides a way to fabricate these new devices to integrate all-optical switching magnetic tunnel junctions with electronic and photonic elements. [ABSTRACT FROM AUTHOR]

Summary: The key obstacle in the realization of multiterminal high‐voltage direct current (MTDC) grids is the lack of existing commercial protection that a device can withstand the DC fault. Although different HVDC circuit breaker technologies have been investigated and demonstrators tested by manufacturers, the innovation of such devices to ensure a reliable protection system has not been proven yet due to the maximum breaking capability limitation especially in MTDC grids. To this, a combination of superconducting fault current limiter (SFCL) technology with a fast DC circuit breaker could bring a solution to this bottleneck. In this work, a new application of an accurate model of resistive‐type SFCL (rSFCL) considering both the electrical and thermal behaviors is proposed to work together with a proactive hybrid DC circuit breaker (PHCB) to fulfill the whole system protection. The viability of the proposed approach is verified under a worst DC fault case‐scenario that imposed in a five‐terminal MTDC meshed grid. The numerical analysis and simulations are carried out using (EMTP‐rv) software, while the obtained results show how significantly the proposed rSFCL can reduce the fault current and enhance the breaking capability. Also, a positive interaction has been observed between the rSFCL and PHCB in terms of design sizing and operation performance. [ABSTRACT FROM AUTHOR]

Hybrid dc circuit breaker (HCB) is an effective device for interrupting dc fault currents in dc grids. Conventional two-port HCB requires too many insulated gate bipolar transistors (IGBTs) in series in its main breaker, resulting in considerable costs. Recently proposed multiport hybrid dc circuit breakers (multiport HCBs, and the number of ports is greater than or equal to 2) interrupt fault currents on multiple lines using only one shared main breaker, significantly reducing the implementation costs but losing some fault handling capabilities. To overcome these obstacles, we propose a novel high-performance economical multiport hybrid dc circuit breaker (MP-HCB) in this article. The topology and its control method are proposed. Due to the designed ring-connection structure, the proposed MP-HCB can avoid dc bus fault, and thus is more reliable. The electrical stresses of the breaker are theoretically analyzed, and the parameters are determined to make the MP-HCB capable of multiple-line faults. Compared with the typical two-port HCB and the existing multiport HCBs, the proposed MP-HCB can achieve full fault current interruption capability with lower costs. To protect a dc node connecting with three lines, the cost of the semiconductors of the proposed MP-HCB is only 1/3 of the typical two-port HCB and 1/2 of the existing multiport HCB. Finally, the performances of the proposed MP-HCB are verified via a four-terminal HVdc system in power systems computer aided design/ electromagnetic transients including DC (PSCAD/EMTDC). [ABSTRACT FROM AUTHOR]

A multifunctional router IC to be included in the nodes of a wearable body sensor network is described and evaluated. The router targets different application scenarios, especially those including tens of sensors, embedded into textile materials and with high data-rate communication demands. The router IC supports two different functionality sets, one for sensor nodes and another for the base node, both based on the same circuit module. The nodes are connected to each other by means of woven thick conductive yarns forming a mesh topology with the base node at the center. From the standpoint of the network, each sensor node is a four port router capable of handling packets from destination nodes to the base node, with sufficient redundant paths. The adopted hybrid circuit and packet switching scheme significantly improve network performance in terms of end-to-end delay, throughput and power consumption. The IC also implements a highly precise, sub-microsecond one-way time synchronization protocol which is used for time stamping the acquired data. The communication module was implemented in a 4-metal, $0.35~\mu \text{m}$ CMOS technology. The maximum data rate of the system is 35 Mbps while supporting up to 250 sensors, which exceeds current BAN applications scenarios. [ABSTRACT FROM AUTHOR]

This brief describes a high-speed optoelectronic receiver implemented in 65 nm CMOS technology. The receiver utilizes only two clock phases instead of the four conventionally used in a quarter-rate clocking system. This two-clock phase system is enabled by a passive silicon photonic split and delay structure that eliminates the need for a quadrature clock phase generator and all the associated buffers. Moreover, the outputs of the receiver are demultiplexed which further helps reducing power consumption in the digital part of the system. The receiver also employs inter-stage AC coupling and is mounted on a high-speed printed circuit board (PCB). The impact of AC coupling and PCB parasitics is investigated. The functionality of the receiver is validated by high-speed optical measurements. The receiver achieves an error-free transmission (BER < 10−12) up to a data rate of 12.5 Gb/s with an energy efficiency of 1.93 pJ/bit and sensitivity of −4 dBm from a 1 V supply. [ABSTRACT FROM AUTHOR]

Based on three groups of different offset voltages, a bandgap reference (BGR) and power-ON reset (POR) hybrid circuit is implemented in 65-nm CMOS. The BGR using amplifier offset voltage and current matching, and the POR using offset voltage comparison and loop settling feature, respectively, are proposed. This circuit, with low-quiescent current, not only generates a stable reference voltage independent of voltage and temperature variations, but also provides a high-robust supply-ramp-rate-tolerant power-ON/brown-out reset signal with a hysteretic window of 18–24 mV. Experimental results show that the circuit with line regulations (LNRs) of 2.63%–4.28%/V and temperature coefficients (TCs) of 22–32 ppm/°C across multiple chips has a power dissipation around $2.25~\mu \text{W}$ from a 1-V supply voltage. The circuit achieves a low noise density of 18.5 nV/ $\surd $ Hz at 100-Hz offset frequency and a good figure of merit (FoM) performance. With an active core area of 0.014 mm2, the circuit has fixed reset trip voltages under the supply ramp time of 0.4–100 ms. [ABSTRACT FROM AUTHOR]

The fast raising nature of DC fault currents and sensitivity of high-voltage DC (HVDC) power converters to DC faults is critical protection issues. On the other hand, DC fault current does not meet zero; which causes DC to fault current breaking process become more challenging. Specifically, to protect HVDC grids against DC fault currents, the development of very fast breakers is crucial. This study proposes a DC fault current limiter and breaker, which is able to protect the HVDC system/grid in a very fast and safe manner. The main goal of this study is to enhance the performance of already in the market hybrid DC circuit breakersincluding the magnitude of fault current and breaker operation speed. In the proposed HVDC fault current limiter and breaker, the fault current is limited in two stages by an inductive and resistive current limiter, which drastically decreases the main breaker dissipated energy. The functionality of the proposed HVDC fault current limiter and breaker is mathematically analysed, and then verified by PSCAD and Matlab/Simulink. Finally, simulation results are validated by scaled-down laboratory examinations. [ABSTRACT FROM AUTHOR]

In this article, a new subdomain and magnetic circuit hybrid model (SMCHM) is proposed for on-load field prediction in the surface-mounted permanent-magnet machines. Equivalent current sheets are introduced to represent the nonlinearity effect, whose values are obtained by a magnetic circuit (MC) and correlated with boundary conditions in a subdomain model. The number of reluctances in the MC of the proposed model can be selected flexibly according to the nonlinearity effect. Instead of sectorial tooth in the conventional subdomain model, parallel tooth is considered in the proposed model to improve the accuracy. The SMCHM can accurately calculate the flux density distributions and electromagnetic performance considering the heavy nonlinearity effect under the load conditions with fast computation speed. The finite-element analysis is performed to validate the proposed model, which shows an excellent agreement between them. A prototype machine is manufactured to further prove these predictions. [ABSTRACT FROM AUTHOR]

In order to study application of hybrid excitation in the magnetic gear composite motor, a series hybrid excitation composite motor with adjustable flux was proposed． It’s based on the principle of flux modulation and hybrid excitation structure． The model of double stator and middle rotor was established． By introducing hybrid excitation on the outer stator, in this structure the principle of flux modulation was combined with the concept of hybrid excitation, which realizes the purposes of low speed, high torque and flux-adjustment． In order to obtain a more stable output torque, the relevant structural parameters of the motor were optimized． The influence of the motor parameters on the relevant characteristics was obtained， and the structural parameters of the motor were determined． The field distribution, air gap flux density， no-load back EMF and output torque of the motor with different DC excitation current were calculated by the two-dimensional finite element method, which verifies the working principle of the motor． The obvious adjustment function of DC excitation to the internal magnetic field of the motor was obtained, which shows the feasibility and rationality of the motor structure. [ABSTRACT FROM AUTHOR]

Resistive random-access memory (ReRAM) has several attractive features such as high storage density and high switching frequency with low power consumption. It is hence regarded as the most promising nonvolatile memory material. However, a memristor, which is a primitive component of the ReRAM-based memory, has much lower write endurance. Hence, an error-correcting code (ECC) circuit is indispensable for realizing reliable ReRAM storage. Accordingly, we propose a hybrid CMOS/memristor-based ECC circuit. In the proposed circuit, the blocks with high-frequency write operations are implemented using the conventional CMOS technology and the other blocks are implemented using the memristors to maintain a balance between the area overhead and reliability. Through numerical experiments, we demonstrate that the proposed ECC circuit achieves smaller area and higher reliability than the full memristor-based ECC circuits and achieves much smaller area while preserving the reliability compared with the full CMOS-based ECC circuits. [ABSTRACT FROM AUTHOR]

Current implementations of quantum logic gates can be highly faulty and introduce errors. In order to correct these errors, it is necessary to first identify the faulty gates. We demonstrate a procedure to diagnose where gate faults occur in a circuit by using a hybridized quantum-and-classical K-Nearest-Neighbors (KNN) machine-learning technique. We accomplish this task using a diagnostic circuit and selected input qubits to obtain the fidelity between a set of output states and reference states. The outcomes of the circuit can then be stored to be used for a classical KNN algorithm. We numerically demonstrate an ability to locate a faulty gate in circuits with over 30 gates and up to nine qubits with over 90% accuracy. [ABSTRACT FROM AUTHOR]

DC fault isolation is one of the main challenges of the HVDC grid. DC fault current can be interrupted within several milliseconds by employing hybrid HVDC circuit breaker. However, this scheme is not cost-effective, especially in meshed HVDC grid. In this paper, a novel integrated HVDC circuit breaker by sharing components is proposed to overcome these drawbacks. Suppose that a converter in a meshed HVDC grid is connected to m DC lines. The integrated HVDC circuit breaker consists of m + 1 ultra-fast disconnectors (UFDs), m + 1 load commutation switches (LCSs), m + 1 mechanical disconnectors (DSs), and only one main breaker (MB) and surge arrester (SA). The behavior of the proposed integrated HVDC circuit breaker is similar to that of the conventional hybrid HVDC circuit breaker. These two kinds of breakers have the same operating time, which means the integrated HVDC circuit breaker is fast enough to clear DC faults. Besides, the IGBT modules in the MB and LCSs of the proposed integrated HVDC circuit breaker are connected in one direction, and the m DC lines share a single MB. Therefore, this scheme is more cost-effective compared to the conventional hybrid HVDC circuit breaker. Moreover, the adjacent lines can still be used to transmit power after DC bus faults. Simulation results on a three-terminal HVDC grid are presented to verify the effectiveness and feasibility of the proposed scheme. [ABSTRACT FROM AUTHOR]

A novel approach utilising the emerging memristor technology is introduced for realising a 2-input primitive XNOR gate. This gate enables in-memory computing and is used as a building block of multi-input XNOR gates. The XNOR gate is realised with eight memristors of two crossbar arrays. The average power consumption of an 8-input XNOR gate is calculated and compared with its counterpart realised with CMOS technology – the XNOR gate consumes less power. ESOP realisation can be directly implemented with XNOR gates. Our simulation results and comparisons show the benefit of the proposed XNOR gate in terms of delay, area, and power. Volistor logic XNOR gate. (a) Circuit diagram of two-input volistor logic XNOR gate. Input voltages are applied to memristors S1 and S2 through horizontal wires Win1 and Win2, and the output which is logical AND of states S1 and S2 is calculated by applying VREAD to vertical wire WXNOR. (b) Block diagram of two-input volistor logic gate. (c) A multi-input volistor logic XNOR gate can be implemented by connecting two XNOR gates though CMOS switches. [ABSTRACT FROM AUTHOR]

Purpose: Several ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobility of the holes, reducing transistor leakage current and eliminating dummy transistors. Design/methodology/approach: This study aims to propose and compare three different comparator-based VCOs that have been implemented using the CNTFETs. The considered circuits are shown to be capable of delivering the maximum 35 tuning frequency in the order of 1 GHz to 5 GHz. A major power thirsty part of the high-frequency ring VCOs is the Schmitt trigger stage. Here, several fast and low-power Schmitt trigger topologies are exploited to mitigate the dissipation power and enhance the oscillation frequency. Findings: As a result of proposed modifications, more than one order of magnitude mitigation in the VCO power consumption with respect to the previously presented three-stage CSVCO is reported here. Thus, a VCO dissipation power of 3.5 µW at the frequency of 1.1 GHz and the tuning range of 26 per cent is observed for the well-established 32 nm technology and the supply voltage of 1 V. Such a low dissipation power is obtained around the operating frequency of the battery-powered cellular phones. In addition, using the p-carrier mobility compensation and enhancing the rise time of the Schmitt trigger part of the CSVCO, a maximum of 2.38 times higher oscillation frequency and 72 per cent wider tuning range with respect to Rahane and Kureshi (2017) are observed. Simultaneously, this topology exhibits an average of 20 per cent reduction in the power consumption. Originality/value: Several new VCO topologies are presented here, and it is shown that they can significantly enhance the power dissipation of the GHz CSVCOs. [ABSTRACT FROM AUTHOR]

Possible sulfur hexafluoride (SF6) gas alternatives have been the focus of research and development in science and industry for many years. After the revision of the European F-Gas regulation 517/2014, the investigation has been even more intensified. One option for an approach for realizing an environmentally friendly switchgear for the high-voltage level is a combination of gas circuit breaker (GCB) and vacuum circuit breaker (VCB) in a series connection. Both switching concepts have advantages: the VCB can withstand very steep rising transient recovery voltages after current zero (CZ), while the GCBs are able to withstand high amplitudes of recovery voltage. In this investigation, the coupling and interaction of a series connection of a VCB and a GCB filled with carbon dioxide (CO2) is experimentally characterized in a basic study. The postarc current of the axial-magnetic-field-type VCB is identified as an important parameter influencing the interaction between both circuit breakers in the series connection and subsequently in the focus of the investigation. The different CZ behavior of a single VCB and a hybrid circuit breaker is compared. The voltage distribution across the two circuit breakers is the main assessment criterion for a series connection. In the first phase after CZ, the postarc current has a dominant influence on the voltage distribution; after that, a transition phase leads to capacitive voltage division phase. In order to control the voltage distribution, both capacitive and resistive voltage controls are investigated. [ABSTRACT FROM AUTHOR]

To perform wearable and continuous health monitoring, epidermal electronics for all kinds of sensing have been developed, yet neither organic nor inorganic materials‐based epidermal devices are able to perform the functions like signal collection, processing, transmission, or power supply. Here, a strategy is reported to build skin‐like hybrid integrated circuits (SHICs) with stretchable sensors and commercial chips for long‐term respiratory monitoring. It can independently perform signal acquisition, processing, converting, and wireless transmission with carrying power supply. Thermal theory model is established to characterize the breathing air's interaction with the sensor, which helps in signal analysis. Respiratory monitoring on human body is tested in diverse daily activities including exercising, dining, drinking, and sleeping with a custom‐developed phone application to record and display the respiratory signal. Results show that the SHIC is of high efficiency and accuracy to track the breath patterns continuously in both static and moving scenarios. Furthermore, the SHIC is a feasible and promising platform that can be extended with multiple sensors or actuators in individualized medical applications and physiological study. [ABSTRACT FROM AUTHOR]

Electronic enclosures often require ventilation and electromagnetic shielding, which have conflicting design requirements. This study proposes a hybrid model, based on circuit model and full‐wave method, for estimating the shielding effectiveness of empty metallic enclosures with ventilation apertures of arbitrary shape or aperture arrays of arbitrary distribution on one side of the enclosures. Such perforated enclosures are split into a perforated plate and semi‐enclosed waveguide that is shorted at the end. The S parameters of the perforated plate are calculated by a full‐wave method and used to estimate the aperture impedance. An equivalent circuit model of a perforated enclosure is established, considering arbitrarily‐positioned apertures, arbitrarily‐chosen observation points, and higher‐order modes. A modified plane wave decomposition technique is adopted to solve the problem of plane waves with arbitrary incident and polarisation directions. In particular, the effects of the electric field components perpendicular to the perforated plate are considered. The efficiency and accuracy of the hybrid model are evaluated by the transmission line matrix method, finite integration technique, experimental observations and existing circuit models. The hybrid model requires much less simulation time than pure full‐wave methods such as the transmission line matrix method. [ABSTRACT FROM AUTHOR]

Hybrid dc circuit breakers (HCBs) usually require a large number of insulated-gate bipolar transistors (IGBTs) with high turn-off capability for series and parallel connections. This requirement entails excessive cost. Compared with IGBTs, integrated gate-commutated thyristors (IGCTs) are another kind of fully controlled power device with high surge current and voltage capability but are low cost. However, the weak turn-off capability of IGCTs hinders their application to high-powered HCBs. On the basis of the complementary advantages of IGBTs and IGCTs, this paper proposes a mixture solid-state switch (MSS) for HCBs that uses the switching action of several IGBTs to create a low-current condition that favors the turning off of large-scale series-connected IGCTs. The MSS topology can significantly reduce cost while maintaining the excellent performance of traditional solid-state switches. This study also introduces two different turn-off modes for MSS, namely, single oscillation and multiple oscillations. Finally, 25 kV/20 kA prototypes in both modes are developed to verify the effectiveness of the MSS topology. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) based high voltage direct current transmission (HVDC) is an effective solution for large-scale renewable power integration over long-distance. In the overhead MMC-HVDC systems, the high voltage DC circuit breakers (DCCB) are implemented to interrupt the DC fault current. Subsequent to fault isolation, the DCCBs are required to automatically re-close to restore power transmission quickly. However, when the DCCBs are re-closed to permanent faults, they will be tripped again, resulting in a high requirement of interruption capacity for DCCBs and second overcurrent strikes on the HVDC systems. To overcome the drawbacks of the conventional auto-reclosing scheme, this paper proposes an adaptive reclosing scheme based on the active pulse injection from the converter associated with the coordination control of hybrid DCCBs. The single-end adaptive reclosing scheme as well as the two ends adaptive reclosing scheme dedicated to two-terminal HVDC systems and meshed DC grids are presented respectively. By applying this method, the location of faults can also be achieved in the case of permanent faults. In order to verify the effectiveness of the proposed adaptive reclosing schemes, extensive simulations have been conducted under PSCAD/EMTDC. [ABSTRACT FROM AUTHOR]

We design a lossless $8 \times 8$ Silicon Photonics (SiPh)/Indium Phosphide (InP) hybrid optical switch. The design consists of an 8-channel InP gain block for coupling to an $8 \times 8$ thermally tuned Mach-Zehnder interferometer-based Banyan switch in a passive SiPh platform. The gain block is an array of eight $1300~\mu \text{m}$ -long semiconductor optical amplifiers (SOAs). We experimentally verified the InP gain block while the SiPh chip is accounted by replacing it with a loss component. The SOA in line with the optical signal path provides a net gain larger than 25 dB to compensate for the inherently large insertion loss of the $8 \times 8$ SiPh optical switch. The total energy consumption of the hybrid optical switch in lossless operation mode is 10.44 pJ/bit at 12.5 Gb/s. [ABSTRACT FROM AUTHOR]

Photonic integrated circuits (PICs) are revolutionizing nanotechnology, with far-reaching applications in telecommunications, molecular sensing, and quantum information. PIC designs rely on mature nanofabrication processes and readily available and optimised photonic components (gratings, splitters, couplers). Hybrid plasmonic elements can enhance PIC functionality (e.g., wavelength-scale polarization rotation, nanoscale optical volumes, and enhanced nonlinearities), but most PIC-compatible designs use single plasmonic elements, with more complex circuits typically requiring ab initio designs. Here we demonstrate a modular approach to post-processes off-the-shelf silicon-on-insulator (SOI) waveguides into hybrid plasmonic integrated circuits. These consist of a plasmonic rotator and a nanofocusser, which generate the second harmonic frequency of the incoming light. We characterize each component's performance on the SOI waveguide, experimentally demonstrating intensity enhancements of more than 200 in an inferred mode area of 100 nm2, at a pump wavelength of 1320 nm. This modular approach to plasmonic circuitry makes the applications of this technology more practical. Chip-scale modular components are important for nanophotonic applications. Here, the authors demonstrate post-processing of a silicon-on-insulator waveguide into an integrated hybrid plasmonic circuit, consisting of a plasmonic rotator and a nanofocusser module, which together result in nanoscale nonlinear wavelength conversion. [ABSTRACT FROM AUTHOR]

A hybrid direct current circuit breaker consisting of electrical contacts connected in parallel with a silicon carbide metal oxide semiconductor field‐effect transistor semiconductor device is capable of operating with low energy loss and high short‐circuit tolerance. It features a short‐duration arc discharge during current commutation; however, how the arc affects the dielectric strength between the contacts is not yet clear. This study conducts a quantitative evaluation of the dielectric strength after a short‐duration arc commutation. It is shown that the dielectric strength decreases after the arc commutation, and the breakdown electric field decreases as the arc duration increases. These results suggest that the existence of metal vapor and an increase in contact erosion caused by the commutation arc lower the dielectric strength of the electric contacts, in addition to the known effects of temperature rise of the contact surface and the air between contacts. © 2020 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [ABSTRACT FROM AUTHOR]

To achieve current balance between parallel‐connected insulated gate bipolar transistors (IGBTs) of a DC microgrid hybrid circuit breaker (DC MHCB), it is a simple and effective method to add impedance in parallel‐connected IGBTs, but this will also affect the vacuum arc commutation of the DC MHCB. The focus of this paper is the effects of adding impedance on vacuum arc commutation characteristics. By constructing a simplified model of vacuum arc commutation in the case of adding impedance, the effect of adding impedance on vacuum arc commutation is theoretically derived. The test circuit of vacuum arc commutation is established, and the effect of adding impedance on vacuum arc commutation in the presence or absence of the externally applied transverse magnetic field (TMF) is investigated using the electrical measure. The theoretical formula and related formulas of the effect of adding impedance on the duration of vacuum arc commutation are obtained. A method combining adding impedance and an externally applied TMF is proposed. The constraint formula for adding impedance during vacuum arc commutation is obtained. The main factors that limit the value of adding impedance are obtained. Research on the effect of adding impedance on vacuum arc commutation characteristics can provide theoretical guidance for the application of the method of adding impedance in a DC MHCB. © 2020 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [ABSTRACT FROM AUTHOR]

This paper proposes a time-domain method to calculate the fault response in multiterminal dc (MTdc) grids and the performance of hybrid dc breakers. The proposed method, based on traveling waves: 1) provides a sound representation of fault performance by considering all created traveling waves; 2) introduces a new approach to estimate the reflection coefficients; and 3) provides an approximation of the worst case fault location. Then, based on the analytical results, three parameters of the hybrid dc circuit breaker, i.e., current limiting reactor, arrester rated voltage, and time delay are optimally selected with respect to maximum overcurrent, maximum overvoltage, fault clearance time, and energy absorption in arresters through multiobjective optimization. Accuracy and performance of the proposed method are evaluated and verified by time-domain simulation studies in the power systems computer aided design (PSCAD)/electromagnetic transients including DC (EMTDC) environment using frequency-dependent models. The results confirm reasonable accuracy of the proposed fault performance calculation and represent a further step towards optimized design of hybrid dc circuit breakers. [ABSTRACT FROM AUTHOR]

We present our hybrid InP to SiN TriPleX integration interface with a novel alignment technique and its application to complex photonic integrated circuits. The integration interface comprises vertical alignment stops, which simplify the alignment process and allow for array integration with the same simplicity as for single dies. Horizontal alignment is carried out by utilizing optical backscatter reflectometry to get an active feedback signal without the need to operate the chip. Thus, typical contacting limitations of active flip-chip alignment are overcome. By using this method, we demonstrate the integration of InP DFB lasers with more than 60 mW of optical power coupled to a SiN waveguide with an averaged coupling loss of -2.1 dB. The hybrid integration process is demonstrated for single dies as well as full arrays. We evaluate the feasibility of the assembly process for complex photonic integrated circuits by integrating an InP gain chip to a SiN TriPleX external cavity. The process proves to be well suited and allows monitoring chip quality during assembly. A fully functional hybrid integrated tunable laser is fabricated, which is capable of full C-band tuning with optical output power of up to 60 mW. [ABSTRACT FROM AUTHOR]

The millimeter wave (mm-wave) frequency band provides exciting prospects for quantum science and devices since many high-fidelity quantum emitters, including Rydberg atoms, molecules, and silicon vacancies, exhibit resonances near 100 GHz. High-Q resonators at these frequencies would give access to strong interactions between emitters and single photons, leading to rich and unexplored quantum phenomena at temperatures above 1 K. We report a 3D mm-wave cavity with a measured single-photon internal quality factor of 3 × 10 7 and mode volume of 0.14 × λ 3 at 98.2 GHz, sufficient to reach strong coupling in a Rydberg cavity quantum electrodynamics system. An in situ piezotunability of 18 MHz facilitates coupling to specific atomic transitions. Our unique, seamless, and optically accessible resonator design is enabled by the realization that intersections of 3D waveguides support tightly confined bound states below the waveguide cutoff frequency. Harnessing the features of our cavity design, we realize a hybrid mm-wave and optical cavity, designed for interconversion and entanglement of mm-wave and optical photons using Rydberg atoms. [ABSTRACT FROM AUTHOR]

In this work, we propose a spin-based voltage comparator using a hybrid spin-CMOS circuit model. In particular, we use a 3T-MTJ (three-terminal magnetic tunnel junction) model with an in-plane magnetic anisotropy (IMA) free layer employing a spin-orbit torque (SOT) based writing scheme in the thermal activation regime to demonstrate a comparator circuit with a resolution close to 50mV. The 3T-MTJ model of the comparator was validated against existing experimental results. In addition, we analyze the delay performance of the comparator along with matching the switching delay of the MTJ with an analytical model. We also discuss potential extensions to the model and general directions for future work. [ABSTRACT FROM AUTHOR]

A direct current (DC) to DC converter with soft switching and high efficiency is developed for industry power units with a wide range of output voltage applications. A series resonant converter is the main circuit on the primary side to accomplish the soft switching characteristics for the active devices and rectifier diodes without switching loss or reverse recovery current loss. To overcome the drawback of the limited operation input or output voltage range in conventional LLC converters, a hybrid resonant converter including a half-bridge circuit and a full-bridge circuit with auxiliary windings is developed to achieve 8:1 (Vo,max = 8Vo,min) output voltage characteristics for a wide range of output voltage applications. To achieve this function, two AC power switches are used in the developed circuit. Since a single-stage hybrid resonant converter is presented instead of a two-stage converter to realize wide voltage range operation, the developed circuit has better efficiency when compared to conventional LLC converters and two-stage DC–DC converters. To confirm the circuit analysis and effectiveness, a prototype with a 400 W rated power was built and tested. [ABSTRACT FROM AUTHOR]

We demonstrate low voltage operating complementary-type inverters based on graphene field-effect transistors (GFETs) by employing an interacting layer of solution-processed fluorocarbon copolymers. These graphene-based inverters with solution-processed aluminum oxide dielectrics exhibit a voltage gain of 0.4 V/V at a low operating voltage of 1.4 V. To enhance p-type and n-type operations for complementary-type inverters, we investigate the tunable device performance of the GFETs with a sandwich structure by comparing their electrical characteristics and Raman spectra with those of pristine GFETs. The sandwich structure contains a graphene channel positioned between the top and bottom films of the fluorocarbon copolymers. We believe that this work can provide a promising route for the emerging concept of graphene inverters for hybrid integrated circuits and logic applications in nanoelectronics. [ABSTRACT FROM AUTHOR]

This article presents a capacitively coupled voltage-controlled oscillator (VCO)-based sensor readout featuring a hybrid phase-locked loop (PLL)- $\Delta \Sigma $ modulator structure. It leverages phase-locking and phase-frequency detector (PFD) array to concurrently perform quantization and dynamic element matching (DEM), much-reducing hardware/power compared with the existing VCO-based readouts’ counting scheme. A low-cost in-cell data-weighted averaging (DWA) scheme is presented to enable a highly linear tri-level digital-to-analog converter (DAC). Fabricated in 40-nm CMOS, the prototype readout achieves 78-dB SNDR in 10-kHz bandwidth, consuming 4.68 $\mu \text{W}$ and 0.025-mm2 active area. With 172-dB Schreier figure of merit, its efficiency advances the state-of-the-art VCO-based readouts by $50\times $. [ABSTRACT FROM AUTHOR]

This brief presents a low-complexity hybrid readout architecture that can extract both timing and amplitude information of the return pulse concurrently for a light detection and ranging radar (Lidar) receiver. To reconstruct the short return pulse, the core circuit of one sampling and storage array with an embedded time-to-digital converter (SSA-TDC) is proposed. Instead of relying on the conventional power-hungry high-speed ADC, it selectively samples the interested return pulse with high speed and stores the voltages for later quantization in the long idle interval. In the preceding stage of the SSA-TDC, the analog front-end circuit cascaded of a narrow-bandwidth transimpedance amplifier, a voltage amplifier, and an equalizer circuit is included. The prototype chip of the eight readout channels is designed and fabricated with the 0.18- $\mu \text{m}$ CMOS process. The active circuit occupies an area of $1200\,\,\mu \text{m}\,\,\times 2100\,\,\mu \text{m}$ , and the power consumption of one single channel is 45 mW with 3.3-V supply. The proposed SSA-TDC has achieved a dynamic error of 180 ps in the experimental study. [ABSTRACT FROM AUTHOR]

In this paper, the overvoltage distributions due to the lightning stroke are analyzed for a 500 kV hybrid OHTL-Cable-GIL circuit beside substation, in which the section length is variable. Corona effect is incorporating in order to estimate the attenuation and deformation of overvoltage's travelling waves on transmission lines near substations. The influence of connecting substations surge arrester, direct, and indirect lightning strokes are investigated. ATP/Electro Magnetic Transients Program(EMTP) simulation program is applied to analyze the lightning overvoltage of a 500 kV hybrid OHTL-Cable-GIL system. It was discovered that OHTL-Cable, OHTL-GIL, and hybrid systems produces lightning overvoltages higher than those of a fully cable system and very likely lower than those of a fully OHTL system with the same transmission lengths. This means that the risk of experiencing high lightning overvoltages and stressing system components is higher in a fully-Overhead Line (OHL)circuit than in a partial or full cable or GIL line. Furthermore, using the Cable with MOSA (Metal Oxide Surge Arrester), the results have more regular voltage waveform at substation entrance; also Hybrid line has the same effect of fully GIL. Finally, the corona has a less attenuation effect of overvoltage reached to substation by about 2.7% in case short length OHTL. [ABSTRACT FROM AUTHOR]

Cu–graphene (Cu-G) hybrid nanointerconnects are promising alternative interconnect solutions for the development of future integrated circuit technology. However, the modeling and simulation of their high-frequency electrical performance remains a challenging problem. To enable the design of complicated Cu-G interconnects, we propose a multiphysics modeling and simulation algorithm to cosimulate Maxwell’s equations, dispersion relation of graphene, and Boltzmann equation. We also develop an unconditionally stable time marching scheme to remove the dependence of time step on space step for an efficient simulation of the multiscaled and multiphysics system. Extensive numerical experiments and comparisons with measurements have validated the accuracy and efficiency of the proposed work. This article has also been applied to predict the crosstalk effect and propagation delay of graphene-encapsulated Cu nanointerconnects. [ABSTRACT FROM AUTHOR]

This paper examines two new bidirectional hybrid dc circuit breaker (CB) topologies for application in meshed dc grids. The goal is to retain performance of hybrid dc CB with bidirectional current interruption while reducing semiconductor count, dc CB size, and weight. The fault current is routed to the unidirectional internal valve using multiple additional ultrafast disconnectors. Operation of both topologies is studied using a 320-kV, 16-kA simulation model, as well as demonstrated on a 900-V, 500-A lab prototype. The control systems are presented and discussed in detail. The low-voltage hardware prototypes verify performance of several new technical and operating solutions in laboratory conditions. A comparison is made with the existing dc CB topologies and performance and reliability compromises of each topology are assessed. The conclusion is that it might be possible to halve the dc CB semiconductor count while retaining same 2 ms opening speed and bidirectional operation. [ABSTRACT FROM AUTHOR]

Due to the ISM band being unlicensed for communication applications, a lot of applications have been developed in this band and a good example is WiFi IEEE 802.11a, b, g, n of Bluetooth. This numeracy of applications motivated this paper. The paper is concerned with the design of a low distortion 20 dBm 2.4 GHz class-J power amplifier (PA) since PAs are indispensable in radio communications. The design is based on the AVAGO ATF-52189 transistor with a transition frequency of 6 GHz. The design is done as a hybrid circuit network realized using microstrip elements and surface mount device (SMD) capacitors. The schematic design and simulation are carried out using Keysight's Advanced Design System version 2016.01. The simulated PA exhibited a drain efficiency of 69% and a power output of 21 dBm. [ABSTRACT FROM AUTHOR]

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient high-performance information processing systems. Its static power is zero because of ac flux bias, and its dynamic power is considerably reduced, thanks to the adiabatic switching of the junctions. The lack of high-density memories in the AQFP logic, however, makes it challenging to realize large-scale information processing systems with the use of pure AQFP circuits. We have been developing a Josephson-CMOS hybrid memory to overcome the memory bottleneck in AQFP digital systems. By utilizing the high sensitivity of the AQFP gate, the output current from CMOS memories can be significantly decreased resulting in the reduction of the power consumption. In this article, we designed and fabricated a low-power area-efficient AQFP-CMOS hybrid field-programmable gate array (FPGA), where a CMOS memory is utilized as a rewritable read-only memory to control the AQFP circuits. The AQFP circuit for the AQFP-CMOS hybrid FPGA is composed of logic blocks, switch blocks, and connection blocks, which are clocked by four-phase excitation currents. The AQFP-CMOS hybrid FPGA is fabricated by using the AIST 10 kA/cm2 Nb high-speed standard process and the Rohm 0.18 μm CMOS process. The area and power consumption of the two-by-two AQFP logic-cell system are estimated to be approximately 6.56 mm2 and 12.4 nW at 5 GHz operations, respectively. The power consumption of the CMOS memory was estimated to be 1.02 μW assuming the CMOS source voltage of 3 mV. We demonstrated the operation of the AQFP-CMOS hybrid FPGA at low speed by combining the AQFP logic and the CMOS memory. [ABSTRACT FROM AUTHOR]

In modern satellite communication systems and airborne repeaters using an APAR, the receiving and transmitting modules usually consist of discrete phase shifters such as hybrid integrated circuits or monolithic circuits. In this paper, we consider an open-frame analog-digital phase shifter module with a 0°–360° phase change that allows ensuring the accuracy of setting the discrete phase to not more than 0.5° based on the domestic control UHF MIS varicaps. An original L-range analog-digital phase shifter with a 0°–360° phase change using a Lange bridge and phase-shifting cells based on four UHF MIS varicaps is proposed. The requirements for the type of volt-farad characteristic and the capacitance overlap coefficient of the MDP-varicap capacitance are determined. Even at the limiting (critical) UHF MIS-varicap frequency not higher than 15 GHz, the proposed scheme of the analog-digital phase shifter allows ensuring the phase shifter loss that is not greater than 1.5 dB in the L-band. The analog-digital phase shifter with a 0°–360° phase change was operated by the digital control board. An 8-bit DAC was used. The division value of the discrete control of the phase shifter is 1.4° at 256 DAC states. The obtained characteristics of the precision analog-digital phase shifter allow concluding on the propects of its use for solving synchronization problems of an active radio target simulator in testing synthetic aperture radars, as well as in the receiving and transmitting modules of a low-element APAR for the L-band. [ABSTRACT FROM AUTHOR]

This article presents a methodology to design a circuit to compensate for process skew by exploiting an inherent dimension-dependent effect of process skew on change in the threshold voltage. We design a voltage reference circuit with a hybrid architecture of bandgap reference (BGR) and CMOS reference, which generates a nominal voltage level of (bandgap - threshold). By compensating the process skew of the threshold term with the proposed dimension-induced effect as well as the temperature dependence, the circuit achieves the simultaneous benefits of BGR and CMOS references. For verification, the circuit was fabricated in three wafers of a 0.18- $\mu \text{m}$ CMOS including extreme slow and fast corners. With an active area of 0.0045 mm2, it consumes 192 pW at room temperature. Measurement from 45 chips (15 chips per wafer) shows untrimmed process/voltage/temperature variations of 0.53%, 0.020%/V, and 33 ppm/°C, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a new self-oscillating mixer (SOM) including a dielectric resonator (DR) antenna fed by a half-mode substrate integrated waveguide (HMSIW) has been proposed using hybrid integrated circuit technique on an FR4 epoxy substrate. The HMSIW resonator with high quality factor and the DR radiator with higher order HEM 13δ mode excitation are responsible for the excellent phase noise performance of the oscillator and the high directivity of the antenna, respectively. The phase noise, estimated LO power, and conversion gain were obtained as −102.5 dBc/Hz at 1 MHz offset, 8.74 dBm at an oscillation frequency of 24.15 GHz, and 8.5 dB, respectively. The figure-of-merit for the oscillator was obtained −172.8 dBc/Hz. [ABSTRACT FROM AUTHOR]

• Bi-directional power electronic switches enable a rapid and flexible conversion between low reactance in non-current-limited mode and high reactance in current-limited mode, suppressing the development of DC faults while achieving current limitation during mechanical switch opening. • The energy absorbed by the MOV is reduced. • DC opening time is shorter. • The proposed DCCB has economic advantages. The use of a DC circuit breaker to open and isolate DC faults in a flexible DC grid is one of the simplest and most reliable methods for handling DC faults. However, current limiting capacity and opening time generally contradict each other in most DC circuit breakers during the DC opening process. Furthermore, current limiting is generally not possible during mechanical switching, which results in higher requirements for the quick-acting nature of protection. To address these issues, a bi-directional current-limited hybrid DCCB topology with fast DC fault opening is proposed. Bi-directional power electronic switches enable a rapid and flexible conversion between low reactance in non-current-limited mode and high reactance in current-limited mode, suppressing the development of DC faults while achieving current limitation during mechanical switch opening, in addition, the time for the arrester to release energy is shortened. The simulation testing system is built on PSCAD/EMTDC, using the Zhangbei Flexible DC Grid project as the engineering background. Comparative analysis of numerous test results demonstrates that the proposed DCCB topology has low DC breaking voltage and current stress, short breaking time, and certain economic benefits. [ABSTRACT FROM AUTHOR]