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This letter analyzes the velocity-field relationship of AlGaN/GaN HFETs via Monte Carlo simulation. This method is based on complete scattering mechanisms such as polarized coulomb field scattering (PCF scattering), polar optical phonon scattering, acoustic deformation potential scattering, inter-valley phonon scattering, and piezoelectric scattering. It is found that the gate bias voltage affects the PCF scattering intensity and the PCF scattering intensity influences the drift velocity under a high electric field. A decrease in peak steady-state drift velocity is observed for our fabricated AlGaN/GaN HFETs from ${1.335}\times {10}^{{5}}$ m/s at $\text{V}_{\text {gs}} =$ 0 V to ${1.23}\times {10}^{{5}}$ m/s at $\text{V}_{\text {gs}} =-3$ V as the gate voltage becomes more negative. When combined with the velocity-field relationship obtained from Monte Carlo simulations, the calculated current-voltage characteristics of AlGaN/GaN HFET devices are in good agreement with our experiment results. The electron saturation drift velocity deviation of AlGaN/GaN HFETs from the Monte Carlo simulation of the GaN material is attributed to the presence of PCF scattering in AlGaN/GaN HFETs. In the study, we provide strong support for the accurate modeling of AlGaN/GaN HFETs. [ABSTRACT FROM AUTHOR]

In this article, an analytical thermal conductivity model considering the degradation caused by the different phonon scattering mechanisms is presented for studying the self-heating effects (SHEs) in ultrathin body and buried oxide (UTBB) silicon-on-insulator (SOI) MOSFETs. By allowing for phonon-boundary and phonon–electron scattering, as well as tuning the surface roughness, the model enables accurate predictions for silicon films of different thicknesses over a wide temperature range. In order to apply the temperature-dependent self-built thermal conductivity model to the technology computer-aided design (TCAD) electrothermal simulation, a piecewise fitting, and equivalent strategy is developed by using the zero points (ZPs) and extreme points (EPs) of the first- and second-order discrete differentials of the model. The results show that the modified model is closer to the experimental data from literature studies than the default TCAD model in predicting the thermal conductivity distribution of the SOI-structure. Furthermore, the TCAD simulation results with our modified model show the same trend as that with its default model in predicting the performance degradation of UTBB SOI devices due to SHEs, such as the degradation of carrier mobility in the channel and the increase of subthreshold swing (SS). [ABSTRACT FROM AUTHOR]

A pump–probe system with a subnanosecond pulsed laser is expected to be a compact and inexpensive transient spectroscopic system that enables nondestructive and noncontact evaluations of the physical properties. However, an improvement in the sensitivity and a theoretical model to complement the measurement signal are necessary to obtain the transient signal precisely because of the low sensitivity and large time resolution. We have developed a highly sensitive pump–probe system with a subnanosecond pulsed laser that combines signal amplification based on surface plasmon resonance (SPR) in this study. An integrated theoretical model of the transient response obtained by a subnanosecond pump–probe under the SPR condition was proposed. Our model consisted of the profile descriptions of the used pulse source, temperature change, generated thermoelastic stress, estimated permittivity change in the metal film, and estimated reflectivity change. The theoretical estimations in the time domain and the incident angle dependence were compared with those of the experimental results to verify our theory. As a result, the estimations were well in agreement with the experimental results. Moreover, the signal-amplification mechanism based on SPR was discussed using our theory. The amplification was caused by the broadening of the resonant curve of SPR and the shift of the resonant angle, which seemed to come from the increase in the electron–phonon scattering rate and the thermal expansion of the metal film, respectively. A clear mechanism of SPR-based signal amplification of the subnanosecond pump–probe was identified through experimental and theoretical approaches. [ABSTRACT FROM AUTHOR]

A novel TreeFET architecture as a combination of stacked nanosheets and additional fin interbridges between nanosheets can enhance ION per footprint. The straight sidewalls of interbridges requires {110} sidewalls, which can be fabricated using n+ Ge/Ge0.95Si0.05/Ge epitaxial layers with co-optimization of wet etching. The TreeFET with {110} interbridges has ION per footprint of $870~\mu \text{A}/\mu \text{m}$ at VOV=VDS=0.5V (2.1X of the referenced 3 stacked nanosheets). To minimize the impurity scattering in the interbridges, the 400 °C annealing is used to drive phosphorus in interbridges into the nanosheets, while the low source/drain resistance is still maintained. The increasing ION down to 77 K indicates that the phonon scattering dominates, and the impurity scattering is minimized in the interbridge channels. [ABSTRACT FROM AUTHOR]

1/f noise provides essential information on the interface trapping effect as well as the scattering mechanism in transistors. In this work, a systematic 1/f noise study has been carried out on the recessed-gate enhancement-mode (E-mode) GaN MOS-HEMTs under electrical and thermal stress together with the depletion-mode (D-mode) counterpart. Low-frequency (1–1000 Hz) measurement has been performed at room (25 °C) and elevated (100 °C) temperatures at different carrier densities at the drain bias of 2 V and 10 V. The results show the E-mode device has much better noise characteristics under high voltage and high temperature compared with the D-mode counterpart. Moreover, charge-noise model reveals that the improved noise behavior of the E-mode device at high density and high drain bias at 100 °C originating from the energy band alignment at high biases, where the D-mode device suffers from extra charge trapping scattering in the gate edge near the gate-to-drain access region.

The galvanomagnetic properties [magnetoresistivity (MR) and Hall Effect] and resistivity at temperatures from 2 to 300 K in magnetic fields of up to 9 T as well as optical characteristics (real and imaginary parts of the complex permittivity, optical conductivity, and reflectivity) at room temperature were studied. It was shown that the temperature dependence of the electrical resistivity has a “metallic” type and is quadratic at low temperatures (< 60 K) that can be caused by the “electron–phonon–surface” interference scattering mechanism in WTe2. Whereas an applied magnetic field induces a minimum in the temperature dependence of the resistivity at low temperatures that shifts to a higher temperature with increasing field, one of the possible explanation of which is the transition from high to weak effective magnetic fields. The MR increases with the magnetic field according to the quadratic law, reaching 1750% at 2 K, which is due to the compensation of charge carriers in WTe2. The Hall effect studies showed that the majority charge carriers are electrons with the concentration of $\sim 10^{19}$ cm−3 and mobility of 7500 cm2/ $\text{V}\cdot \text{s}$ at 2 K. At the same time, optical investigations did not reveal the feature characteristics of metals. The optical conductivity spectrum is a broadband centered at 3.4 eV and formed by interband transitions. The presence of peaks in the infrared region indicates the formation of low-energy gaps in the band spectrum of WTe2. The obtained data on the real and imaginary parts of the complex permittivity also evidence the absence of a contribution from free carriers up to 0.2 eV. The optical characteristics are shown to be in good agreement with the data on electronic transport properties. The revealed features are a manifestation of the topological nature of the material. [ABSTRACT FROM AUTHOR]

This study simulates and compares symmetric and asymmetric MoS2 nanosheet transistor structures. The results show that the asymmetric MoS2 nanosheet transistor achieves higher current density and better gate control, and thus, this structure is optimized to meet the current density requirement for low-power applications in the International Roadmap for Devices and Systems (IRDS). Dielectric materials of Al2O3 and HfO2 are investigated, and equivalent oxide thicknesses ranging from 0.8 to 2 nm are analyzed. Transistors with Al2O3 as the dielectric exhibit better performance than those with HfO2 due to the lower level of remote phonon scattering. The gate length and underlap region are scaled down from 14 to 5 nm and from 7 to 1 nm, respectively, in an attempt to further enhance the ON-current. The substoichiometric metal oxide AlOx is used to induce more electrons in the undoped MoS2 channel. AlOx increases the ON-current with no gate control degradation. After optimization, the transistor demonstrates a subthreshold swing of 62.3 mV/dec, a drain-induced barrier lowering (DIBL) of 21.6 mV/dec, and a current density of $495 ~\mu \text{A}/\mu \text{m}$ with a supply voltage of 0.65 V. Compared with Si gate-all-around transistors, the MoS2 nanosheet transistor exhibits excellent gate control, good electrostatics, and comparable current density. [ABSTRACT FROM AUTHOR]

InGaZnO thin-film transistors (IGZO TFTs) adopting p-type Si with different doping concentrations as the gate electrodes are fabricated to study the effects of the electrical coupling between the gate electrode and the gate dielectric on the carrier mobility in the IGZO channel. In general, the carrier mobility is found to increase with increasing gate doping concentration because more holes in the gate electrode can screen/suppress the remote phonon scattering of the gate dielectric on the channel electrons (the screening effect). However, for certain gate doping concentrations, the carrier mobility surprisingly shows a decrease instead (the anti-screening effect). This has three implications: 1) like the free electrons in the n-Si gate electrode of OTFT, the holes in the p-Si gate electrode can oscillate about the dopant ions; 2) when the oscillation frequency is close/equal to the atomic vibration frequency of the high- ${k}$ gate dielectric, the resulting resonance between the gate electrode and the gate dielectric can enhance the atomic vibration of the latter to increase the remote phonon scattering on the channel carriers of the IGZO TFTs; and 3) the anti-screening effect could occur in any MOS-based devices. [ABSTRACT FROM AUTHOR]

In this letter we investigate phonon-dominated mobilities for carriers in a diamond field effect transistor with a cubic Boron Nitride (cBN) overlayer. We investigate the intra-subband scattering due to interaction of electrons with acoustic phonons, treated properly as quantized surface acoustic Rayleigh waves, and include, for the first time, the interaction with remote polar phonons originating in the cBN overlayer. We conclude that the surface acoustic phonon scattering is the dominant mechanism limiting the mobility of electrons for temperatures below 375 K. [ABSTRACT FROM AUTHOR]

In this work, the low-frequency noise (LFN) characteristics of hafnium-zirconium oxide (HZO) ferroelectric field-effect transistors (FeFETs) with and without high-pressure forming gas annealing (HPA) treatment are investigated. The origin of $1/ {f}$ noise in the FeFET without HPA is changed from carrier number fluctuation to Hooge’s mobility fluctuation after wake-up due to the remote phonon scattering from the polarized HZO. Also, Hooge’s parameter is increased by the program/erase (P/E) cycling-induced stress. On the contrary, only the correlated mobility fluctuation is increased after the wake-up in the FeFET with HPA. Furthermore, the LFN of the FeFET with HPA shows robustness to P/E cycling-induced stress after the wake-up, showing superb endurance performance. [ABSTRACT FROM AUTHOR]

In this study, the inversion layer mobility characteristics in Si-face 4H silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with nitrided and phosphorus-doped gate oxides were compared using Hall effect measurements. The inversion layer mobility was evaluated by applying a body bias and changing the temperature. The carrier scattering properties were determined for elevated temperatures (i.e., 473 K), at which point the impact of Coulomb scattering decreases and that of phonon scattering increases. The phonon-limited mobility of these MOSFETs was almost the same when plotted as a function of the effective normal electric field in the inversion layer, possibly representing the nature of the thermally grown SiO2/SiC interface. On the basis of this finding, the effect of phonon scattering was separated from the inversion layer mobility. The MOSFETs exhibited a remarkable difference in Coulomb scattering: the MOSFETs with phosphorus-doped gate oxide exhibited a more rapid increase in Coulomb-limited mobility with increasing surface carrier density than did the MOSFETs with nitride gate oxide. This resulted from the effective suppression of Coulomb scattering in the inversion layer, which is one of the reasons why phosphorus-doped gate oxide achieves higher inversion layer mobility than nitrided gate oxide. These results show that the inversion layer mobility of SiC MOSFETs can be modeled using a conventional framework of phonon, Coulomb, and surface roughness scattering. Therefore, the suppression of Coulomb scattering is key to further improving the inversion layer mobility of SiC MOSFETs. [ABSTRACT FROM AUTHOR]

In this article, we present a surface-potential-based approach to model the bias-dependent effective velocity observed in AlGaN/GaN high-electron-mobility transistors (HEMTs) due to optical phonon scattering. Our model precisely reproduces the progressive decrease in the saturation velocity in GaN HEMTs with increasing gate voltages, as reported in the literature, which is predominantly due to the scattering of electrons, forming the high-density two-dimensional electron gas (2DEG), by optical phonons at high overdrive voltages. We show that this dependence differs from the traditional mobility degradation models in terms of its impact on the device current–voltage (I – V) characteristics and illustrate how the inclusion of a velocity saturation model also provides the model users with an additional handle for parameter extraction. The model is explicit and, by virtue of its Simulation Program with Integrated Circuit Emphasis (SPICE) compatibility, is readily implemented in the industry-standard Advanced SPICE Model for HEMTs (ASM-HEMTs) model and has been validated against experimental dc I – V and RF S-parameter measurements of an in-house GaN device. [ABSTRACT FROM AUTHOR]

The effects of the Si-substrate doping concentration on electrical characteristics of back-gate (BG) and top-gate (TG) MoS2 field-effect transistors (FETs) are investigated. The experimental results show that MoS2 FETs fabricated on different-concentration Si substrates using the same processing have similar interface characteristics and surface roughness of gate dielectric but exhibit different carrier mobility, and the higher the doping concentration, the higher the carrier mobility. This is because the carriers in Si substrate can screen the phonon scattering from the low-energy surface optical phonon produced by the soft Hf-O bonds in HfO2 dielectric, which will couple with the carriers in MoS2 channel, resulting in the reduction of the mobility, and the higher the Si-substrate concentration, the better the screening effect. Also, it is found that the BG dielectric scattering will impact on the mobility of the TG transistor, which causes a similar change trend of carrier mobility to that of the BG MoS2 FET as the Si-substrate concentration increases. Therefore, it can be revealed that the Si-substrate concentration has an important influence on the carrier mobility of MoS2 FETs, and the high Si-substrate concentration is beneficial for fabricating high-performance BG and TG MoS2 FETs. [ABSTRACT FROM AUTHOR]

In this article, we report the temperature-dependent transistor characteristic of Epi-Gd2O3/AlGaN/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT) and compare its properties with that of AlGaN/GaN metal-Schottky high electron mobility transistor (HEMT) grown on 150 mm Si (111) substrate. Introducing an epitaxial single crystalline Gd2O3 between the metal gate and AlGaN barrier not only improves the gate leakage current significantly but also enhances its thermal stability. We observe that there is no significant change in the gate leakage current even at 473 K compared to that measured at room temperature (RT) (298 K), and this is also evident in the transistor’s subthreshold behavior at 473 K. We have determined the electric field within the Gd2O3 as well as AlGaN and investigated the leakage conduction mechanism through Gd2O3. The ION/IOFF of the transistor was measured as high as ~108 even at 473 K with the lowest VTH shift (91.4 mV) with temperature. Our measurements also confirm the presence of polar optical phonon scattering, which directly affects the 2-D electron gas (2DEG) mobility at high temperatures and thus the electrical characteristics of HEMT and MOSHEMT. [ABSTRACT FROM AUTHOR]

We report the characterization of the channel mobility properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) on the heterogeneous β-Ga2O3-on-SiC (GaOSiC) substrate fabricated by an ion-cutting process. The mobility of GaOSiC MOSFETs is significantly improved as the postannealing temperature of Ga2O3 channel increases from 900 °C to 1200 °C. The GaOSiC transistor annealed at 1200 °C exhibits mobility consistent with the β-Ga2O3 donor wafer, which suggests that the defects in Ga2O3 channel induced by the H+ implantation for the ion-cutting step can be eliminated by the high-temperature annealing. As the ambient temperature (Tamb) increases from 0 °C to 150 °C, the mobility within the accumulation regime of GaOSiC MOSFETs decreases with the temperature following a Tamb−1 law, which is limited by the phonon scattering. The results of this work will be critically important for designing the transport properties of the GaOSiC channel, significantly advancing the development of Ga2O3 power devices on high thermal conductivity substrate. [ABSTRACT FROM AUTHOR]

With the development of separation and sorting techniques, highly enriched semiconducting single-walled carbon nanotubes (SWNTs) have become widely accessible, which has led to the rapid growth of high-performance solution-processed SWNT-based thin-film field-effect transistors (TFTs) showing capabilities comparable to the ideal single-SWNT FETs. With such improvements, theoretical studies and detailed analyses of these networks have become necessary. In this work, a model justifying the near-ideal electrical transport in SWNT networks is presented. The field-dependent resistive properties of the networks are calculated using a numerical solver based on the derived individual resistances of SWNTs and the intertube couplings. The model is capable of simulating mixed SWNT networks consisting of both metallic and semiconducting nanotubes of varying chiralities. Our analysis reveals that the high electrical currents in networks could be largely attributed to the suppression of phonon scattering and strong intertube couplings in highly dense SWNT networks (>30–40 SWNTs μm2). Comparisons between the simulated and experimental results indicate good agreement thereby demonstrating the accuracy of the proposed model. [ABSTRACT FROM AUTHOR]

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width (WNSH) and sheets stacking number (N) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors. [ABSTRACT FROM AUTHOR]

In this article, an analytical thermal conductivity model for confined nanochannel in gate-all-around silicon nanowire field-effect transistors (GAA SiNW FETs) is developed by considering the limitations caused by the cross section and length. A geometry dependence of phonon mean free path (MFP) is established for quantitatively analyzing the influence of cross-sectional dimension. Furthermore, the length-induced degradation mechanism is revealed by employing the transverse transportation phonon effective MFP. The results calculated by the model which was verified by published data indicate that the thermal conductivity of confined nanochannel in the GAA SiNW FETs is suffering from a severe degradation compared to that of ultrathin silicon in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. In addition to the suppression caused by the cross-sectional boundaries, the impact of the channel length should be taken into consideration during the modeling of thermal conductivity for accurately evaluating the self-heating effects (SHEs) in GAA SiNW FETs. [ABSTRACT FROM AUTHOR]

This article presents a comprehensive analysis of the characteristics of an n-type monolayer MoS2 piezoelectric field-effect transistor (PZFET) based on a realistic model that includes scattering by intrinsic phonons, remote phonons, and charged impurities. By employing the density-functional theory (DFT), first, we evaluated the effect of the uniaxial compressive out-of-plane strain on the band structure and carrier’s effective masses of a MoS2 monolayer. Thereafter, by solving the linearized Boltzmann transport equation (BTE), the carrier mobility, mean free path, and mean-free-time modulation under different vertical strains in the presence of various scattering mechanisms are computed. By the use of the computed properties, we assessed the characteristics of the PZFET, in which the vertical strain is induced in the monolayer MoS2 channel from the piezoelectric layer (π-layer). The results indicate that the studied PZFET in relation to both the ballistic and nonballistic transports is subthermionic [subthreshold swing (SS) smaller than 60 mV/decade] with a relatively large ION/IOFF ratio. The results based on the realistic model indicate that a monolayer MoS2 PZFET enables the scaling of the channel length and the supply voltage beyond the conventional field-effect transistors (FETs). [ABSTRACT FROM AUTHOR]

We have observed and analyzed the 1/ƒ1+α noise in transient leakage current through a metal–insulator–metal stacked high-k capacitor of TiN–ZrO2–TiO2–TiN. The ZrO2 and TiO2 films, formed by atomic layer deposition, are polycrystalline and show geometrical variety at interfaces (i.e., grain boundaries). Two types of transient leakage current are observed: 1) the monotonically decreasing component with power law dependence and 2) the uneven component having power law dependence. To analyze the uneven component in time domain, we assumed that the power law decay occurs due to a gradual change in the redistribution of electrons between interfaces of ZrO2–TiN and ZrO2–TiO2. The frequency-domain analysis shows that the 1/ƒ1+α noise comes from the transient leakage of direct tunneling and trap-assisted tunneling (α > 0). In particular, the noise in the uneven component, the random telegraph noise part ((α ~ 1), relates to local trap states in a grain boundary affected by phonon scattering. In addition, the analytical method we developed in this article shows an excellent agreement with various measurements of the transient gate leakage current. [ABSTRACT FROM AUTHOR]

Recent studies show disordered materials such as amorphous silicon (a-Si), in spite of their low mobility, can efficiently amplify photocurrent via carrier multiplication process. Detectors with a thin (~40nm) a-Si multiplication layer has demonstrated single photon sensitivity at high speed under room temperature. It is believed that the abundance of bandtail states that cause low mobility of the amorphous materials actually contribute to the detector’s superior performance because carrier impact ionization involving these states, which can be modeled by donor-acceptor pairs (DAPs), relax the k-selection rule of the many-body carrier multiplication process. Our paper presents a theoretical framework to calculate the carrier multiplication process in a-Si or other disordered materials involving DAPs. Our analysis also establishes the relations between detector characteristics and key parameters such as the density of band tail states, layer thickness, and applied electric field. DAP assisted carrier multiplication rate is computed first. Carrier multiplication coefficients for electrons and holes under given applied field are then calculated using a trial distribution function that satisfies both the continuity equation and the energy balance equation. Our analysis shows that thinner a-Si gives rise to higher multiplication efficiency than thicker a-Si because of its higher carrier kinetic energy when the layer thickness is shorter than the length of energy relaxation by phonon scattering. Using the calculated carrier multiplication coefficients, voltage dependent gain of the device is computed and the results agree well with the measured results of a-Si cycling excitation process (CEP) detectors. [ABSTRACT FROM AUTHOR]

This article reports on the extraction of the electron velocity as a function of gate bias from N-polar GaN deep recess high-electron-mobility transistors (HEMTs) designed for mm-wave power amplification. Bias-dependent small-signal S-parameter measurements are used to obtain small-signal equivalent circuit parameters, which are applied to a transit delay model. The model accounts for fringing capacitance to arrive at an electron velocity associated with the transit of the physical gate length. A peak electron velocity of 1.4 × 107 cm/s was obtained at a drain current of 700 mA/mm corresponding to a channel charge density of 0.3 × 1013 cm−2. At higher current, the velocity slowly decreased with the electron velocity crossing below 107 cm/s at 1.8 A/mm. This behavior was found to be in good agreement with a previously proposed model based on optical phonon scattering at the source injection point. An analysis of the delay components is used to provide guidance for the factors influencing the device performance. [ABSTRACT FROM AUTHOR]

In the past couple of years, GaN-based vertical FETs have been explored to complement their potential logic applicability along with its well-known advantages in high-power and RF applications. In this article, the performances of short-channel gate-all-around (GAA) GaN vertical nanowire MOSFETs, fabricated for a possible low-voltage logic application, have been investigated via simulation, assuming the multilevel trapping effects at the gate interface and the self-heating effects. The simulation results reveal that shallow traps at the interface increase the OFF-state current, the subthreshold swing, and the drain-induced barrier lowering, while deep traps at the interface lower the ON-state current and cause the threshold voltage instability. When the gate voltage is higher than the flat-band voltage of the nanowire channel in the saturation region of operation, the mobility degradation, related to the self-heating, becomes significant due to the increased incorporation of the optical phonon scattering. [ABSTRACT FROM AUTHOR]

The effects of high temperature on an asymmetrically doped vertical pillar-type metal-oxide-semiconductor field-effect transistor (MOSFET) were investigated. An asymmetrically doped source and drain (S/D) can be easily formed in a vertical pillar-type FET due to the unique pillar structure. When high temperature is applied to the asymmetric S/D of a vertical pillar-typed silicon nanowire, it affects mobility and carrier injection differently. It decreases mobility by phonon scattering for heavily doped S and intermediately doped D. In contrast, it enhances carrier injection for intermediately doped S and heavily doped D. Thus the ON-state current (ION) shows opposite dependencies at high temperature. This tendency was verified by electrical measurements and supporting simulations. [ABSTRACT FROM AUTHOR]

In this article, we performed gated four-probe measurements on amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) to extract their intrinsic mobility and contact resistance as functions of gate voltage and temperature. The abnormal degradation of field-effect mobility was observed in a-IGZO TFTs both at high gate voltage and at high temperature. Results showed that contact resistance played a major role in mobility degradation at high gate bias, whereas band-like transport (phonon scattering) accounts for mobility degeneration at high temperature. We proposed a novel method, which exposed the contact regions to ultraviolet (UV) ozone. The mobility was boosted from 23 to 30 cm2/Vs, nearly 40% increment at high gate bias. [ABSTRACT FROM AUTHOR]

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with HfLaO as high-k gate dielectric have been fabricated, and p-type silicon wafers with resistivities of 0.001 ~ 0.002, 0.005, 0.02 ~ 0.021 and $5\sim 10\Omega \cdot $ cm are used as their gate electrodes. The carrier mobility of the samples show an increase with increasing gate acceptor concentration, indicating that the TFT performances are affected by the hole concentration in the gate electrode. The HfLaO gate dielectric is highly polarizable and so produces surface-optical phonons, which can scatter the electrons in the IGZO channel to reduce their mobility. Therefore, this work directly demonstrates that the holes in the gate electrode can have a screening effect to suppress this remote phonon scattering of the gate dielectric on the channel carriers, just like the electrons in the metal gate, ITO gate and n-silicon gate of field-effect transistors. [ABSTRACT FROM AUTHOR]

We propose two different designs of p-type piezoelectric (PE) FinFETs (PE-FinFETs) covering low-power (LP) and high-performance (HP) operation modes. LP mode PE-FinFETs achieve a lower OFF-current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) and HP mode PE-FinFETs result in a larger ON-current (${I}_{ \mathrm{\scriptscriptstyle ON}}$). These two different modes are achieved by simply changing the outer PE-gates bias. The advanced nonequilibrium Green’s function (NEGF) approach self-consistent with six-band ${k}\cdot {p}$ method including phonon scattering is used to investigate the device performance. The gate voltage-controlled strain is analytically derived from the principle of PE effect. The HP and LP PE-FinFETs are studied, respectively, and the impacts of channel material, device orientation, and phonon scattering on both HP and LP PE-FinFETs are comprehensively investigated. The simulation results show that Ge is superior to Si for both LP and HP PE-FinFETs. With a supply voltage of 0.5 V, ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ of Ge LP mode PE-FinFETs is reduced by 18 times, and Ge HP mode PE-FinFETs obtain 50% ON-current enhancement. ${I}_{ \mathrm{\scriptscriptstyle ON}}$ (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) is unchanged for LP (HP) mode PE-FinFETs. Phonon scattering not only causes a large ${I}_{ \mathrm{\scriptscriptstyle ON}}$ degradation but also changes the optimal device orientation for both Si and Ge HP mode PE-FinFETs compared to their counterparts without phonon scattering. [ABSTRACT FROM AUTHOR]

Bottom-gated pentacene organic thin-film transistors (OTFTs) were fabricated on p-type and n-type Si wafers with different resistivities, with NdTaON as a high- ${k}$ gate dielectric. Although the pentacene grain size and dielectric surface roughness were nearly the same for all the samples, the carrier mobility improved with decreasing resistivity for both types of OTFTs (p-gate and n-gate), indicating that similar to the electron concentration, the hole concentration in the gate electrode can also affect the carrier mobility. This is attributed to the remote phonon scattering of the high- ${k}$ gate dielectric on the channel carriers, which can be screened by the holes in the gate electrode. The p-gate and n-gate samples with the lowest gate–electrode resistivity of $0.005~\Omega \cdot $ cm achieve the highest mobility of 1.15 and 1.37 cm $^{{2}}/\text{V}\cdot \text{s}$ , respectively. Moreover, for the same gate-doping concentration, the p-gate sample shows lower mobility than the n-gate sample. This is likely because under a negative gate voltage (${V}_{g}$), the p-gate is depleted to make the actual ${V}_{g}$ smaller than the applied ${V}_{g}$ , thus resulting in a lower extracted carrier mobility. In addition, such a depletion effect leads to a lower hole concentration near the gate–electrode/gate–dielectric interface, thus weakening the gate screening effect on the remote phonon scattering. [ABSTRACT FROM AUTHOR]

A theoretical investigation on the phonon-limited mobility in intrinsic n-type few-layer indium selenide (InSe) double-gate devices for temperature T > 100 K is presented. The temperature-dependent mobility curves measured by quantum Hall effect are reproduced successfully by invoking the scatterings by acoustic phonon, homopolar optical phonon, longitudinal optical phonon via the deformation potential coupling, and the Fröhlich interaction. In InSe, the Fröhlich interaction plays the dominant role in determining the mobility. Additionally, simulated thickness-dependent mobility provides physical insight into the mobility degradation below 30 nm. [ABSTRACT FROM AUTHOR]

Bottom-gated pentacene organic thin-film transistors with LaTiON gate dielectrics annealed at two different temperatures are fabricated on n+Si wafers. Although atomic-force microscopyresults indicate a smoother dielectric surface and larger pentacene grains for the sample annealed at 400 °C, this sample shows lower carrier mobility than the one annealed at 200 °C. Moreover, the crystallinity of the gate dielectrics is not a key factor in the degradation of the carrier mobility because both dielectrics remain amorphous according to TEM. However, the TEM results show that the sample annealed at 400 °C has a thicker dielectric/Si-gate interlayer. The resultant increase in gate electrode-to-dielectric distance weakens the gate screening of the remote phonon scattering, thereby degrading the mobility of the carriers in the pentacene channel. This effect can be further supported by two similar samples fabricated on n-Si wafers, in which the gate electrode with lower electron concentration has a reduced screening effect on the remote phonon scattering and results in a larger reduction in mobility for the 400 °C-annealed sample with thicker interlayer. [ABSTRACT FROM AUTHOR]

In this paper, the effect of electron–phonon scattering on the negative differential resistance of graphene nanoribbon p-n junctions is investigated. The results show that the optical phonon scattering, due to inelasticity, significantly increases the valley current such that the peak-to-valley ratio decreases several orders of magnitude compared to ballistic approximation. It also shifts up the valley voltage. The former effect manifests itself more in structures with a smaller band gap and better ballistic characteristics. We show that it remains remarkable in different lengths of the transition region and severely affects the performance of the device. The results also show that phonon scattering plays a significant role even in ultrascaled nanodevices. [ABSTRACT FROM AUTHOR]

Bottom-gated pentacene organic thin-film transistors (OTFTs) with NdTaON as high-k gate dielectric have been fabricated on substrates with different resistivities: $0.005~\Omega ~ \cdot $ cm, $0.3~\sim ~0.9~\Omega ~ \cdot $ cm, and $1~\sim ~5~\Omega ~\cdot $ cm for n-Si wafers, and $35~\Omega $ /sq for ITO-coated glass. On the three n-Si substrates, the dielectric surface roughness and pentacene grain size are nearly the same, but the carrier mobility of the OTFTs show an obvious increase with decreasing resistivity, indicating that the gate electron concentration can affect the device performance. Despite the much larger dielectric surface roughness and smaller pentacene grain size, the OTFT on the ITO-coated glass shows the highest carrier mobility. These effects are attributed to remote phonon scattering on the channel carriers, which has been strongly screened by the electrons in the gate electrode. According to the measurement on the mobility degradation at high temperature, the remote phonon scattering is determined to be the dominant factor affecting the carrier mobility. As a result, the OTFT on ITO glass can achieve a high carrier mobility of 2.43 cm2/V $\cdot $ s and a small threshold voltage of −0.10 V. [ABSTRACT FROM AUTHOR]

We study the noncoherent transport due to electron–phonon (e-ph) interaction in graphene nanoribbon (GNR) field-effect transistors (GNRFETs) using nonequilibrium Green’s function method in mode space. Phonon dispersion calculations in conjunction with the e-ph interaction computations show that in an armchair GNR, only a small number of phonon modes are coupled to the carriers. Our simulation shows that under a threshold gate voltage, the drain–source current is diminished by the low-energy phonons such as acoustic phonon modes and radial-breathing-like phonon modes, while at great biases of the gate, the current drop is essentially due to high-energy optical phonon modes. The effect of drain voltage on scattering process is discussed, which shows that at higher drain voltages, the ballisticity decreases. We also explore the phonon scattering dependence on the dimensions of GNRFET channel. In larger width ribbon, the impact of phonon scattering decreases. The channel with a length of 30 nm is ballistic up to 90%, and only when its length is increased to approximately 180 nm, transport becomes semiballistic, which infers to an effective mean free path of ~200 nm. [ABSTRACT FROM AUTHOR]

In recent years, 3-D GaN-based transistors have been intensively studied for their dramatically improved performance. However, thermal analysis of such devices is often oversimplified using the conventional Fourier's law in thermal simulations. In this aspect, accurate temperature predictions can be achieved by coupled phonon and electron Monte Carlo (MC) simulations that track the movement and scattering of individual phonons and electrons. Based on these MC simulations for the transistor region and the Fourier's law analysis for the rest of the chip, accurate electrothermal simulations are carried out on a nanowire-based GaN transistor to reveal the temperature rise in such devices. [ABSTRACT FROM AUTHOR]

In this letter, the carrier transport mechanism in a high-mobility zinc oxynitride (ZnON) thin-film transistor (TFT) is investigated by analyzing the gate bias and temperature dependence of conductance and intrinsic field-effect mobility ( \mu \mathrm {FEi}) in the subthreshold and above-threshold regions, respectively. The measured drain currents increase with a temperature and show a thermally activated Arrhenius-like behavior in the subthreshold region. The experimental results are well explained using a Meyer–Neldel rule, which suggests that the trap-limited conduction is the dominant carrier transport mechanism in the ZnON TFT in the subthreshold region. The carrier transport mechanism in the ZnON TFT in the above-threshold region is investigated by examining the gate overdrive voltage ( V\mathrm {OV}) and temperature dependence of \mu \mathrm {FEi} . \mu \mathrm {FEi} extracted from the ZnON TFT decreases with an increase in V\mathrm {OV} and temperature, which suggests that the phonon scattering is the most probable mechanism limiting \mu \mathrm {FEi} in the ZnON TFT in the above-threshold region. [ABSTRACT FROM PUBLISHER]

The distinct negative differential resistance (NDR) mechanism arising from interlayer angular rotation in three-terminal graphene-BN heterostructures, as a function of both the twisting angle and the gate bias, is simulated and analyzed. Analytical expressions for the positions of the NDR peaks in the $I$ – $V$ characteristics are developed. To capture the degradation of peak-to-valley ratios observed in experiment at room temperature, electron–phonon scattering has been added to the simulation and good agreement with experiment is achieved. Our simulation also shows a robust preservation of NDR feature when temperature increases. [ABSTRACT FROM PUBLISHER]

A new nonballistic analytical model for the intrinsic channel region of MOSFET-like single-walled carbon-nanotube FETs (CNTFETs) with ohmic contacts has been developed which overcomes the limitations of existing models and extends their applicability toward high bias voltages needed for analog applications. The new model comprises an improved description of the electron–phonon scattering mechanism, considering the accumulation of electrons at the bottom of conduction subband due to back scattering by optical phonons. The model has been justified by a Boltzmann transport equation solver. The simulation results are found to be in agreement with the experimental data for highly doped CNTFETs. [ABSTRACT FROM PUBLISHER]

Low-frequency noise (LFN) in double-gate (DG) In–Ga–Zn–O (IGZO) thin-film transistors (TFTs) is studied to investigate the origin of performance improvement. We found that thinning down the IGZO film enhances such improvements. With 7-nm IGZO, the mobility is raised by a factor of 3.77, and the subthreshold slope is reduced to 0.17 V/decade from single-gate to DG mode. Device simulations show that bulk transport inside IGZO film emerges as the two gates field effects get coupled. The LFN results reveal a transport transition from surface to bulk and disclose the superior bulk transport that experiences slight phonon scattering with a small Hooge parameter \alpha H = 4.44 \times 10^{\mathrm {-3}} , whereas the surface transport undergoes serious charge trapping with surface trap densities about 2 \times 10^11 eV ^-1 cm ^-2 . [ABSTRACT FROM PUBLISHER]

In this paper, we report, for the first time, that surface roughness scattering is not necessarily the dominant scattering mechanism in the high-normal-field region of Ge nMOSFETs. This statement is quite different from the well-recognized situation in Si MOSFETs. In Ge(100), phonon scattering is dominant in the high-field region. Thus, it is difficult to increase the high-normal-field mobility in Ge(100) nMOSFETs by controlling the interface roughness. In contrast, because Ge(111) and Ge(110) are free of intervalley phonon scattering, the high-field mobility in Ge(111) and Ge(110) nMOSFETs could be enhanced by the Ge interface engineering. Furthermore, different from that in Si nMOSFETs, mobility limited by surface roughness scattering in Ge nMOSFETs shows a strong temperature dependence due to the valley occupancy change of electrons. The results in this paper should facilitate efforts to increase the high-normal-field mobility in Ge nMOSFETs. [ABSTRACT FROM AUTHOR]

Electron transport in Si double-gate junctionless transistors (JLTs) is simulated on the basis of the multisubband Monte Carlo method, considering acoustic phonons, intervalley phonons, ionized impurities (IIs), and surface roughness (SR) scattering. It is demonstrated that JLTs can actually minimize the mobility degradation caused by SR scattering and improve the current drivability. On the other hand, II scattering is confirmed to degrade the current drivability compared with conventional MOSFETs with an intrinsic channel. However, the performance degradation in JLTs due to II scattering is shown to be insignificant, owing to the screening effect of free carriers and the forward scattering properties of high-speed carriers. Furthermore, by extracting a backscattering coefficient, the screening effect and the forward scattering properties are shown to more mitigate II scattering as the gate voltage increases. [ABSTRACT FROM AUTHOR]

Hole mobility in strained ultrathin body InSb-on-insulator (InSb-OI) devices is calculated by a microscopic approach. The anisotropic valence band structures, in consideration of quantum confinement, are obtained via solving the six-band $k\cdot p$ Schrödinger and Poisson equations self-consistently. Hole mobility is calculated using the Kubo–Greenwood formula accounting for nonpolar acoustic and optical phonons, polar optical phonons, and surface roughness scatterings. The models are calibrated and verified with experimental data. The influences of body thickness and strain effect, including both biaxial and uniaxial strains, are investigated in InSb-OI devices. Our results indicate that mobility degradation occurs in both single-gate (SG) and double-gate (DG) mode when body thickness scales down below a certain range. Moreover, mobility in the DG mode outperforms that in the SG for thick body thickness, but loses its superiority over SG for extremely thin body. Compressive strain is favorable to hole mobility. Furthermore, more enhancement is achieved by uniaxial strain than biaxial strain. [ABSTRACT FROM AUTHOR]

The introduction of dipoles into a polymer can enhance dipole-induced scattering which tends to "cool" hot electrons and thereby inhibits runaway of hot electrons. A theoretical analysis of electron scattering by dipoles and phonons is presented which provides the basis for explaining temperature dependence of breakdown field on the basis of the dominant scattering process as a function of temperature. By performing electron mobility calculation in non-polar and polar polymers, a quantitative correlation between chemical composition and intrinsic breakdown strength can be established. Calculation of dipole scattering limited electron mobility can be used to assess the effect of dipole scattering on the intrinsic breakdown field of polymers. [ABSTRACT FROM AUTHOR]

An empirical model for the effective electron mobility in silicon nanowires (SiNWs) is presented. The model is based on published mobility data from numerical simulations of electron transport in SiNWs with different cross sections. Both phonon scattering and surface roughness scattering as well as the impact of the effective vertical field are considered. A comparison with a variety of experimental mobility data from the literature shows that the model can be treated as a reference for benchmarking different NW technologies. The effective field dependence is modeled by a simple expression making our mobility model very efficient for the use in numerical device simulators or in analytical MOSFET models. [ABSTRACT FROM AUTHOR]