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Extending the wireless power transfer range in miniaturized remotely powered micro-devices is a big challenge due to the very small effective area and low gain of the mm-sized antenna utilized in the micro-devices, which limits the harvested RF energy. This paper presents a method for increasing the separation distance between an external energy source antenna as a transmitter (TX) and micro device antenna as a receiver (RX) beyond 10 cm by utilizing various TX antennas, including a conventional loop antenna, multiple patch antennas, and a rectangular cavity antenna, and a 2-turn double-sided square loop RX antenna, sized 1.2mm x 1.2mm on FR4 substrate, which can be mounted on top of a CMOS SoC. The performance of the wireless power transfer system is evaluated and compared in different scenarios. At the 434 MHz ISM band, the results indicate that the highest peak power transfer efficiency of -20 dB and the highest harvested DC voltage of 4 V through an 8-stage Dickson RF-DC converter are obtained inside the rectangular hollow cavity sized 49.6cm x 49.6cm x 30.4cm, as TX, with an input TX power of 20 dBm. Furthermore, the multiple patch antennas have a power transfer efficiency of -39 dB and a harvested DC voltage of 2.5 V at a distance of 10 cm with an input TX power of 37 dBm. The specific absorption rate of both cases stays below the limits established by IEEE., Funding Agencies|Swedish Foundation for Strategic Research (SSF) [RMX18-0066]

This paper presents a nerve stimulation system implementation that contains full-wave rectifier-based energy harvester switching at 13.56MHz to generate stimulation current for accelerating the regeneration time of recovering damaged nerve. Reconfigurable eight-bit driver cells provide the selective option of controlling the stimulation current from as low as 4 mu A up to 0.92mA. The design is implemented in a standard 180nm CMOS process with a core area of 0.22mm(2) excluding a 3.6nF on-chip integrated capacitor which occupies 0.34mm(2) of the chip area. The fabricated chip is measured and characterized with coupled AC input amplitude of 2.2V and a driver load of 1k Omega. Furthermore, the measurement results verify the rectified DC output of 2V which implies a conversion ratio of 0.91.

This paper proposes a dynamic range (DR) extension technique based on a two-step conversion for high-sensitivity multi-element pseudo-resistive (MEPR) transimpedance amplifiers (TIA). In optical biomedical sensors targeted for fluorescence measurement applications, the front-ends high sensitivity and wide DR are critical for accurately recording cellular variations. In this work, the most significant bits (MSB) are extracted by a 2-bit current digital-to-analog converter (DAC) then the least significant bits (LSB) are extracted by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The current DACs are composed of identical pseudo-resistor (PR) elements used in the TIA feedback to make the MSB extraction robust against the process and mismatch variations. This technique preserves the linearity of the conversion while using the current DACs to improve the DR. The proposed front-end implemented in 65 nm CMOS technology achieves a DR of 72.3 dB with current detection of 1 pA up to 4.13 nA at a sampling rate of 1 kS/s. The total front-end consumes a power of 45 mu w from a 2.5 V supply., Funding Agencies|Swedish Foundation for Strategic Research (SSF) [RMX18-0066]

Energy harvesting is a method that extracts electrical energy from the environment. This paper presents an integrated circuit in 0.35-mu m CMOS that harvests energy from mechanical vibration using a piezoelectric transducer. The circuit applies a bias-flip rectifier to improve the efficiency of the energy extraction. The paper focuses on the design of the key element of the bias-flip rectifier, the zero-crossing detector. It detects the zero crossing of the input current from the piezoelectric transducer and generates the control signals for the bias-flip rectifier. Post-layout simulations show a very low power consumption and high efficiency of the harvester., Funding Agencies|Linkoping University; European Unions Horizon project smart-MEMPHIS [644378]; strategic innovation program Smarter Electronics Systems a joint venture of Swedens innovation agency; Swedish Research Council Formas; Swedish Energy Agency [2015-01305]

Modern high data rate communication use modulated signals with large peak-to-average power ratios (PAPR). The power efficiency of such signals when using common types of power amplifiers (PAs) can be rather low, as they require a large output back-off (OBO) to be reasonably linear. In this paper, a recent new architecture for improving the efficiency at OBO, the load modulated balanced amplifier (LMBA), is studied by circuit and EM simulations for realization in a 180 nm CMOS process, including matching networks and power combiners (90 degrees couplers). The selected structure is a Doherty-like LMBA, where the control signal for the load modulation is generated by a separate, integrated amplifier. Simulated with on-chip inductor losses and center frequency of 2 GHz, the peak PAE at full output power (24 dBm) is 34.8%. At 6 dB OBO, the LMBA gives a PAE of 32.6% compared to 23.2% for a reference amplifier without load modulation, and load optimized for peak PAE, an absolute PAE improvement of 7.4% or a relative PAE improvement of 31.9%. The main limitation of the integrated CMOS LMBA appears to be losses in the passive components needed for matching and load modulation.

This paper presents a pipeline analog-to-digital converter achieving 7.7 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used with asymmetrical biasing of the pMOS and nMOS transistors and digitally controlled binary-weighted assisted capacitor chain for calibration in the gain stage. It results in an increased closed-loop linearity and a THD of-53.1 dB while allowing symmetrical layout, transconductances, and parasitic effects. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary-weighted capacitor chain at gate of transistors which makes the power consumption of gain stage correction be avoided in digital domain. With a core power dissipation of 47.5 mW and an FoM of 0.355 pJ/conv-step, high sample rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency. © 2020 IEEE.

Inductively powered 99% accurate implantable temperature sensor is designed, characterized and the findings are presented in this paper. The implantable sensors deliver a continuous temperature reading to external storage or readout devices via Near Field Communication interface. A 2.76 mu H rectangular inductive coil printed on a thin biocompatible plastic substrate is designed to establish the coupling link through NFC interface with external readout devices. A commercially available wide range temperature sensor chip is mounted along with the developed inductive coil on the same plastic substrate. For 50 samples, the received signal strength indicator, temperature accuracy and statistical distribution of measurement levels is investigated. Comparison of predetermined temperature in a controlled temperature and humidity chamber versus the temperature reading from the developed sensors proves a 99% accuracy., Funding Agencies|Swedish Foundation for Strategic Research (SSF)Swedish Foundation for Strategic Research

This paper presents three self-oscillating multilevel time-interleaved switched-capacitor DC/DC converters implemented and taped-out in 0:18-mu m CMOS targeting microwatt power levels. Two of the converters are step-up with ratios of 1:2, 1:3, and 1:4, and one is a step-down with ratios of 2:1, 3:1, and 4:1. They all regulate the output voltage towards a targeted reference removing the need for a separate regulator. Aimed for use in vibration energy harvesting systems, the converters have a wide combined input voltage range of 450 mV to 20 V. The low voltage step-up converter operates from an input voltage of 475 mV and has a peak measured power efficiency of 82.2 % with an area of 0.62 mm(2). The medium voltage step-up converter operates from an input voltage of 700 mV and has a peak power efficiency of 74.5 % and an area of 0.53 mm(2). Lastly, the step-down converter works with input voltages up to 20 V and achieves a peak power efficiency of 68.7 % with an area of 0.55 mm(2)., Funding Agencies|European Unions Horizon project smart-MEMPHIS [644378]

Many integrated circuit functional blocks, such as data and power converters, require timing and control signals consisting of complex sequences of pulses. Traditionally, these signals are generated from a clock signal using a combination of flip-flops, latches and delay elements. Due to the large internal switching activity of flips-flops and due to the many, effectively unused, clock cycles, this solution is inefficient from a power consumption point of view and is, therefore, unsuitable for ultralow-power applications. In this paper we present a method to generate non-overlapping control signals without using flip-flops or a clock. We propose to decode and translate the internal states of a ring oscillator into the desired control signal sequence. We show how this can be achieved using a simple combinatorial logic decoder. The proposed architecture significantly reduces the switching activity and the capacitive load, largely reducing the consumed power. We show an example implementation of a 9-bit SAR logic utilizing our proposed method. Furthermore, we show simulation results and compare the power consumption of the example SAR implementation to that of a functionally identical flip-flop-based state-of-the-art ultralow-power SAR. We were able to achieve a 5.8x reduction in consumed power for the complete SAR and 8x for the one-hot generation sub-part., Funding Agencies|European Unions Horizon project smart-MEMPHIS [644378]; strategic innovation program Smarter Electronics Systems a joint venture of Swedens innovation agency, Swedish Research Council Formas; Swedish Energy Agency [2015-01305]

In Magnetic Resonance Imaging (MRI) scanners Radio Frequency (RF) signals are important to accurately excite target tissues. RF signals depend on Digital-to-Analog Converters (DAC) output which depends on sequence numbers issued from control room. This paper presents a sigma-delta modulator (SDM), followed by a DAC architecture that can be reconfigured while an MRI scanner is operating and pipelining is not required. The reconfigurable SDM is implemented in a 65nm CMOS technology and operates at an oversampling ratio (OSR) of 64 times. The modulator clocks at 2 GHz frequency with a 1.2-V supply voltage. The modulator occupies an area of 2 9 x 3 2 sq.mu m and consumes 319.1 mW. The proposed SDM-DAC is well-suited for the RF transmitter in the MRI scanner. The reconfigurability feature allows to select different resolutions for various types of RF pulses and can thereby target specific tissues more accurately. (1)

This paper describes the design and implementation of an asynchronous clock generator which has been used in a 14-bit two-stage pipelined SAR ADCs for low-power sensor applications. A self-synchronization loop based on an edge detector was utilized to generate an internal clock with variable phase and frequency. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Thereafter, three separate asynchronous clock generators were implemented to create the control signals for two sub-ADCs and the gain-stage between. Finally, a 14-bit asynchronous two-stage pipelined SAR ADC was designed and simulated in 0.18 mu m CMOS. Detailed pre-layout circuit simulations show that the ADC achieves a SNDR of 83.5 dB while consuming 2.13 mu W with a sampling rate of 10 kS/s. The corresponding FoM is 177.2 dB.

This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters from 0.35-mu m CMOS process. The comparison results show that the proposed gain-stage is more power efficient than SC integrator. To verify the analysis, two types of gain-stage, SC integrator and multi-stage CCP, were simulated in 0.35-mu m CMOS process. Simulation results show that the three-stage CCP achieves a gain of 7.9 while only consuming 1.1 mu W with the gain bandwidth of 178.7 kHz. But the SC integrator consumes 1.58 times more power than CCPs to reach the similar gain and gain bandwidth.

Aiming to alleviate operational transconductance amplifiers (OTA), this paper describes the design of a capacitive charge pump (CCP) gain-stage for a two-stage pipelined SAR ADCs suitable for low-power sensors. An analog buffer is inevitable to prevent the charge sharing between the capacitive stages. In this work a simple source follower has been used as the analog buffer, showing sufficient linearity and significant power reduction compared to earlier work where a unity-gain OTA was used. To verify the solution, a CCP gain-stage with source follower has been implemented in design of a 14-bit two-stage pipelined SAR ADC in 0.18 mu m CMOS. Detailed circuit simulations show that the ADC achieves a SNDR of 83.0 dB while consuming 1.8 mu W at a sampling frequency of 10 kHz., Funding Agencies|Swedens innovation agency; Swedish Research Council Formas; Swedish Energy Agency [2015-01305]; European Union [644378]

In this paper we present results based on measurements of implantable devices which can be powered externally and communicated with using the near-field communication (NFC) infrastructure. NFC allows us to not have a dedicated gateway and intra-body communication to bridge the data from sensors to phone. In our trials, we have used commercially available sub-components and mounted them on a thin plastic with printed interconnections and coated them for bio-compatibility. Devices were implanted in porcine models during one week. We could during this time measure the in-vivo body temperature through skin and subcutaneous tissue ranging in thickness from some mm to a couple of cm. The implanted sensor devices are mounted on thin, printed-electronics plastic sheets where the coils and conductors are designed with different types of materials. The choice of materials is done in order to offer a low-cost solution to read out data from in-vivo sensors. We compile measured data, practical results and guidelines, together with theoretical results referring to the design of the implanted inductive NFC coil as well as the energy transfer from one mobile device to another.

This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves −64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuoustime common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68o. Sufficient performance is maintained over process, supply voltage and temperature variations.

This paper presents a fully-differential operational transconductance amplifier (OTA) designed in a 28 nm ultra-thin box and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. An overview of the features of the 28 nm UTBB FDSOI process which are relevant for the design of analog/mixed-signal circuits is provided. The OTA which features continuous-time CMFB circuits will be employed in the programmable gain amplifier (PGA) for a 9-bit, 1 kS/s SAR ADC. The reverse body bias (RBB) feature of the FDSOI process is used to enhance the DC gain by 6 dB. The OTA achieves rail-to-rail output swing and provides DC gain = 70 dB, unity-gain frequency = 4.3 MHz and phase margin = 68ï¿œ while consuming 2.9 μW with a Vdd = 1 V. A high linearity > 12 bits without the use of degeneration resistors and a settling time of 5.8 μs (11-bit accuracy) are obtained under nominal operating conditions. The OTA maintains satisfactory performance over all process corners and a temperature range of [-20oC +85oC].

This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the reference voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 ï¿œW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

This paper presents two novel transmitter architectures based on the combination of radio-frequency pulse-width modulation and multiphase pulse-width modulation. The proposed transmitter architectures provide good amplitude resolution and large dynamic range at high carrier frequency, which is problematic with existing radio-frequency pulse-width modulation based transmitters. They also have better power efficiency and smaller chip area compared to multiphase pulse-width modulation based transmitters.

Harvesting ambient energy, as an alternative power source, tackles the increasing demand for future energy-efficient autonomous sensor systems, especially for applications requiring miniaturisation and distributed sensing such Wireless Sensors Network and Internet-of-Things. A functional energy harvesting system requires addressing simultaneously all the components of the system: the harvester device, the energy storage and the powering management circuits. These components are described through examples of miniaturized kinetic-based harvesting systems for low-power applications with focus on energy harvester, piezoelectric and electromagnetic, respectively., Funding Agencies|European UnionEuropean Union (EU) [644378]; Knowledge Foundation fund ASIS [20140323]; Swedens Innovation Agency, VinnovaVinnova [2017-03725]

We investigate the use of ring counters as phase accumulator in VCO-based ADCs. An experimental phase accumulator is proposed that consists of parallel ring counters designed with latches. The ring counters count both negative and positive input edges and use special decoding of counter output and feedback to obtain Gray code, facilitating sampling of the outputs. The outputs are combined by selecting sequence lengths that in combination realize a residue number system (RNS), significantly reducing the hardware cost for implementing long sequences that would be very costly to achieve with a single ring counter. We discuss the conversion from the parallel cyclic Johnson code sequences, first to RNS, and then to binary. Area and power requirements are evaluated through design of two 8 bit phase accumulators that are synthesized towards a standard cells implementation in a 65 nm bulk CMOS process. Proposed phase accumulator consumes about 2/3 more area and half the power over a reference implementation designed with reflected binary Gray counters.

Digital predistortion (DPD) performance for an IEEE 802.11ac WLAN transmitter in 28 nm CMOS, using 20 and 80 MHz bandwidth with 256QAM modulation, is analyzed under different bandwidth limitations. Due to band-limited conditions in the transmitter chain, the DPD linearization performance may be reduced. For a minimum transmitter error vector magnitude (EVM) requirement of -32 dB (2.5%) for 256QAM modulation, a reduction in the maximum linear output power of 1.6 dB due to bandwidth limitations in the transmitter chain is estimated using simulations and measurement results., Funding Agencies|Strategic Innovation Program "Smartare Elektroniksystem"; joint venture of the Swedish Governmental Agency for Innovation Systems; Swedish Research Council Formas; Swedish Energy Agency

Modular multiplication (MM) based on the residue number system (RNS) is a widely researched area due to the fast arithmetic operations in the RNS. The major drawback of the RNS based MM architectures is their large area because each arithmetic operation is followed by a modular reduction. In this work, the number of modular reductions is reduced and instead the wordlength of some operations is increased to accommodate the intermediate results. The proposed scheme greatly reduces the number of multipliers and achieves a 55% reduction in the hardware complexity. Moreover the delay of the proposed architecture is also significantly lower than the reference architecture.

A VCO-based ADC is designed and synthesized in a 28 nm FDSOI CMOS process to investigate the scaling benefits of all-digital analog-to-digital conversion. A coarse-fine quantizer is used to obtain high energy efficiency. Common patterns of sample errors at the multi-phase VCO output are identified and mitigated. Final design indicates an ENOB of 13.4 and a Walden FoM of 4.3 fJ/step over a 5 MHz bandwidth while sampling at 150 MHz, according to schematic simulation of the synthesized netlist.

MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.

An all-digital delay locked loop (DLL) for use in an analog video front end (AFE) is presented. The DLL is designed for a wide input frequency range of 40-300 MHz to cater to a range of different video standards currently in use. The proposed DLL has a closed loop architecture that tracks PVT variations and locks to the input signal in a maximum of nine clock cycles. At its output, the DLL generates 32 uniformly distributed phases of the input clock to provide an optimal sampling point for the analog to digital conversion of the input signal in the AFE.

The linear-drift memristor model, suggested by HP Labs a few years ago, is used in this work together with two window functions. From the equations describing the memristor model, the transfer characteristics of a memristor is formulated and analyzed. A first-order estimation of the cut-off frequency is shown, that illustrates the bandwidth limitation of the memristor and how it varies with some of its physical parameters. The design space is elaborated upon and it is shown that the state speed, the variation of the doped and undoped regions of the memristor, is inversely proportional to the physical length, and depth of the device. The transfer characteristics is simulated for Joglekar-Wolf, and Biolek window functions and the results are analyzed. The Joglekar-Wolf window function causes a distinct behavior in the tranfer characteristics at cut-off frequency. The Biolek window function on the other hand gives a smooth state transfer function, at the cost of loosing the one-to-one mapping between charge and state. We also elaborate on the design constraints derived from the transfer characteristics.

MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.

MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.

MEMS-based piezoelectric energy harvesters are promising energy sources for future self-powered medical implant devices, low-power wireless sensors, and a wide range of other emerging ultra-low-power applications. However, the small form factors and the low vibration frequencies can lead to very low (in μW range) harvester output power. This makes the design of integrated CMOS rectifiers a challenge, ultimately limiting the overall power efficiency of the entire power management system. This work investigates two different fully integrated rectifier topologies, i.e. voltage doublers and full bridges. Implemented in 0.35-μm, 0.18-μm, and 65-nm CMOS technologies, the two rectifier architectures are designed using active diodes and cross-coupled pairs. These are then evaluated and compared in terms of their power efficiency and voltage efficiency for typical piezoelectric transducers in such ultra-low-power applications which generate voltages between 0.27-1.2 V. Furthermore, analytical expressions for the rectifiers are verified against circuit simulation results, allowing a better understanding of their limitations.

Synthesizable all-digital ADCs lead to reduced design cost and design time as well as to low cross-technology porting costs. VCO-based ADC is an attractive candidate for the synthesis of ADCs using standard cells. However, a VCO, which is controlled by an analog input signal, is difficult to implement using standard digital circuits. Supply controlled ring oscillators using static CMOS inverters are used in prior works. In this work, an alternative VCO built using NAND gates is proposed for use in synthesizable converters. The circuit is demonstrated by employing it in an ADC synthesized from an HDL description. Transistor level simulation of the resulting netlist using the Spectre simulator shows that a performance of 10 bit ENOB over a 10 MHz bandwidth can be achieved after digital correction, using the proposed VCO.