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A novel dual-bias circuit structure increases a power amplifier's video bandwidth while reducing the memory effect, thereby improving its linearity. A Doherty power amplifier (DPA) operating in the 5G communication band (3.4 to 3.6 GHz) and incorporating this circuit achieves a saturated output power of 43 to 44 dBm with a saturated drain efficiency greater than 70 percent. Drain efficiency is 51 to 55 percent at 6 dB power back-off and greater than 43 percent at 8 dB back-off. As output power reaches 42.7 dBm, the adjacent channel leakage ratio (ACLR) is less than -46 dBc combined with digital predistortion (DPD). [ABSTRACT FROM AUTHOR]

The article discusses a broadband, high efficiency, class J power amplifier (PA) design uses the relationship between drain efficiency and the ratio of drain-source capacitance to load impedance. Topics include to control harmonics at the output of a conventional class AB power amplifier to achieve high efficiency; and work analyzes the trend of drain-source capacitance with the drain-source voltage and proposes a circuit to compensate transistor output.