Search

JPL, under sponsorship from the NASA Office of Advanced Concepts and Technology, has been developing a second-generation solid-state image sensor technology. Charge-coupled devices (CCD) are a well-established first generation image sensor technology. For both commercial and NASA applications, CCDs have numerous shortcomings. In response, the active pixel sensor (APS) technology has been under research. The major advantages of APS technology are the ability to integrate on-chip timing, control, signal-processing and analog-to-digital converter functions, reduced sensitivity to radiation effects, low power operation, and random access readout.

This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.

Recent research results regarding the investigation of CMOS active pixel image sensors (APS) are reported. An investigation of various designs for the pixel, including photogate devices of various geometries and photodiode devices has been performed. Opto-electronic performance including intra-pixel photoresponse maps taken using a focused laser scanning apparatus are presented. Several imaging arrays have also been investigated. A 128 x 128 image sensor has been fabricated and characterized. Both p-well and n-well implementations have been explored. The demonstrated arrays use 2 micron CMOS design rules and have a 40 x 40 micron pixel pitch.

A family of CMOS-based active pixel image sensors (APS) that are inherently compatible with the integration of on-chip signal processing circuitry is reported.