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35 results on '"Geraldo F"'

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1. Memory-Centric Computing: Recent Advances in Processing-in-DRAM

2. Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance

3. Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis

4. PUMA: Efficient and Low-Cost Memory Allocation and Alignment Support for Processing-Using-Memory Architectures

5. MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing

6. Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions

7. Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis

8. PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips

9. DaPPA: A Data-Parallel Framework for Processing-in-Memory Architectures

10. ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation

11. TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systems

12. ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems

13. RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory

14. Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud

15. Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory

16. Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture

17. An Experimental Evaluation of Machine Learning Training on a Real Processing-in-Memory System

18. Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices

19. Machine Learning Training on a Real Processing-in-Memory System

20. Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases

21. Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures

22. Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Cooperation

23. Casper: Accelerating Stencil Computation using Near-cache Processing

24. Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study

25. Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-in-Memory Hardware

26. Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks

27. HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes

28. SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM

29. DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

30. Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture

31. pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables

32. Polynesia: Enabling Effective Hybrid Transactional/Analytical Databases with Specialized Hardware/Software Co-Design

33. Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models

34. SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM

35. A Modern Primer on Processing in Memory

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