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We demonstrate an Nb$_{2}$O$_{5}$/$\beta$-Ga$_{2}$O$_{3}$ metal-insulator-semiconductor (MIS) hetero-junction diode with Nb$_{2}$O$_{5}$ as the high-k dielectric insulator for more efficient electric field management resulting in enhanced breakdown characteristics compared to a $\beta$-Ga$_{2}$O$_{3}$ Schottky barrier diode. The Nb$_{2}$O$_{5}$ dielectric films were grown using atomic layer deposition and exhibited a high dielectric constant of 50. The high dielectric constant resulted in a 5$\times$ lower electric field at the metal/dielectric interface in the MIS diode compared to the metal/$\beta$-Ga$_{2}$O$_{3}$ interface in the Schottky barrier diode. With good electron conduction in forward bias enabled by the negative conduction band offset of Nb$_{2}$O$_{5}$ w.r.t $\beta$-Ga$_{2}$O$_{3}$, the MIS design led to a 3$\times$ improvement in the reverse blocking voltage with a slight trade-off in the specific on-resistance. Overall, a 3.3$\times$ increase in the power figure of merit was observed (3.25 MW/cm$^2$ for the Schottky diode and 10.8 MW/cm$^2$ for the MIS diode). A detailed analysis of the energy band line-up, and the forward and reverse current transport mechanisms are also presented using analytical modeling and 2-D TCAD simulations., Comment: The following article has been submitted to 'Journal of Applied Physics' and the link will be updated if it gets published

$\beta$-Ga$_{2}$O$_{3}$ based enhancement mode transistor designs are critical for the realization of low loss, high efficiency next generation power devices with rudimentary driving circuits. A novel approach towards attaining a high positive flat band voltage (V$_{fb}$) of 10.6 V in $\beta$-Ga$_{2}$O$_{3}$ metal-oxide-semiconductor capacitors (MOSCAPs), with the ability to fine tune it between 3.5 V to 10.6 V, using a polycrystalline AlN charge trap layer has been demonstrated. This can enable enhancement mode operation over a wide doping range. Excellent V$_{fb}$ retention of ${\sim}$97% for 10$^{4}$ s at 55 $^{\circ}$C was exhibited by the gate stacks after charge trapping, hence reducing the requirement of frequent charge injection cycles. In addition, low gate leakage current density (J$_{g}$) for high negative gate voltages (V$_{g}$${\sim}$-60 V) indicates the potential of this gate stack to enable superior breakdown characteristics in enhancement mode transistors., Comment: Single file (Manuscript and Supplementary material combined) of 19 pages. Total 5 and 4 figures in manuscript and supplementary material, respectively