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1. Laser Processing For 3D Junctionless Transistor Fabrication

Author

Bosch, D., Alba, P. Acosta, Kerdiles, S., Benevent, V., Perrot, C., Lassarre, J., Richy, J., Lacord, J., Sklenard, B., Brunet, L., Batude, P., Fenouillet-Beranger, C., Lattard, D., Colinge, J. P., Balestra, F., and Andrieu, F.

Subjects
Physics - Applied Physics
Abstract

To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.

Published
2020

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