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This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased $\Sigma \Delta $ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter, thus maximizing the use of digital circuits while keeping only the RC network and the comparator as the sole analog blocks. Analysis and behavior level simulations of the DFLL have been carried out to guide the optimization of the long-term stability and frequency accuracy of the timer. High frequency accuracy and a $10\times $ enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of $\Sigma \Delta $ modulation to improve the DCO resolution. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm2). The proposed timer achieves the excellent energy efficiency (0.57 pJ/cycle at 417 kHz at 0.8-V supply) over prior art while keeping excellent on-par long-term stability (Allan deviation floor < 20 ppm) and temperature stability (33 ppm°Cat 0.8-V supply). [ABSTRACT FROM AUTHOR]

An energy-efficient fast start-up method for crystal oscillators is presented, which enables aggressive duty-cycled operation of IoT radios to minimize overall power consumption. A digitally controlled crystal oscillator using the proposed start-up technique in 90-nm CMOS is presented. Thanks to the dynamically adjusted load, the negative resistance is boosted, achieving a $13\times $ start-up time reduction and an overall power of $95\mu \text{W}$ for a 24-MHz crystal oscillator at 1 V. A fully autonomous feedback loop detects the oscillators envelop and adjusts the load capacitance at start-up. Thanks to the low-power start-up circuits, both the start-up time and the start-up energy are reduced. In addition, the robustness and versatility of the proposed method is verified by measuring quartz crystals with different frequencies and quality factors, as well as measuring against temperature, supply voltage, and load capacitance variations. [ABSTRACT FROM AUTHOR]

Memory, especially DRAM, is one of the candidates to be considered in three-dimensional integrated circuit (3-D IC), and in particular, to be heterogeneously stacked with a system on chip (SOC) for mobile applications. Even though the memory is tested and repaired beforehand, the known good die (KGD) can become bad during the integration process. Traditional schemes may not be able to redo the repair and obtain a known good stack (KGS), let alone unused spares be reused. We propose an off-chip repair scheme to deal with the inaccessibility from outside of the memory die. Using a through silicon via (TSV) to access the redundancy control circuit (RCC), we reactivate the unused spares by overwriting their states as if the corresponding fuses are blown. Even when the row or column, which has already been repaired, is damaged again, we are able to replace it with a new spare. Our simulation using a 65 nm process technology shows that the maximum timing penalty of the off-chip repair is only 93ps, compared to the on-chip method. The area overhead is estimated to be 490 \mu\ m^2 per fuse set by using a 5 \mu\ m diameter TSV process. Most importantly, the yield improvement of a two-die stacked memory can be over 50% with yield excursion reduced to 8%. [ABSTRACT FROM PUBLISHER]

A nonlinear system being composed of multiadaptive notch filters in parallel is introduced to track the sinusoidal components of an almost periodic signal and estimate their frequencies and amplitudes. An almost periodic nonlinear dynamic system for estimation of frequencies is achieved after the existence of a slow integral manifold is proved and results in a nonlinear autonomous system with averaging method employed. Three types of local stability of the autonomous system, the exponential stability in isolated equilibrium point and the semistability on center manifold and the ultimate boundedness under unknown periodic disturbance, are respectively investigated. The transient performance is affected by frequency adaptive gain independent of bandwidth parameter. The validity of the proposed algorithm is verified by simulation results. [ABSTRACT FROM PUBLISHER]

This paper presents a novel die-to-die clock synchronization method that is independent of the inter-die wire delay. Through a 2-Phase All-Digital Delay Locked Loop (2P-DLL) and a Dual Locking Mechanism (DLM), this method can be used to maintain a global clock signal between two dies in a 3-D IC, and thereby enabling the synchronous 3-D IC design methodology. Unlike previous designs, ours does not need to replicate the delay of the inter-die clock wire. This property can make our scheme more adaptive to various 3-D technologies and more robust to PVT variation. Such a method has several other benefits. For example, it can accommodate the ever-increasing process variation easily through its silicon tracking ability. Simulation results indicate that it can support clock signals running up to 2.8 GHz. Silicon measurements of a test chip in a 90 nm CMOS technology show that the phase error can be locked constantly to less than 9.6 ps at a clock frequency of 600 MHz, with a peak-to-peak jitter of 9.778 ps and a power consumption of only 1.8 mW. [ABSTRACT FROM PUBLISHER]