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This paper focuses on speeding up NTRU - one of the lattice-based finalists of the NIST PQC competition - by improving the ring multiplication. The Number Theoretic Transform (NTT), Toom-Cook, and Karatsuba are the most commonly used algorithms for implementing NTRU. In this paper, we propose Toeplitz matrix-vector product (TMVP) based algorithms for multiplication for all parameter sets of NTRU. We implement the proposed algorithms on ARM Cortex-M4. The results show that the TMVP-based multiplication algorithms we propose are more efficient than the others in the literature in most cases. Our algorithm for ntruhps2048509 outperform the Toom-Cook and NTT methods in the literature by 25.4% and 21.5%. We also observe the impact of these improvements on the overall performance of NTRU. We speed up the key generation, encryption, decryption, encapsulation, and decapsulation algorithms of ntruhps2048509 by 12.5%, 14.3%, 17.7%, 3.9%, and 14.7%, respectively, compared to state-of-the-art implementation. Moreover, our algorithms require less stack space than the others. [ABSTRACT FROM AUTHOR]

Modern NVIDIA GPU architectures offer dot-product instructions (DP2A and DP4A), with the aim of accelerating machine learning and scientific computing applications. These dot-product instructions allow the computation of multiply-and-add instructions in a single clock cycle, effectively achieving higher throughput compared to conventional 32-bit integer units. In this paper, we show that the dot-product instruction can also be used to accelerate matrix-multiplication and polynomial convolution operations, which are widely used in post-quantum lattice-based cryptographic schemes. In particular, we propose a highly optimized implementation of FrodoKEM wherein the matrix-multiplication is accelerated by the dot-product instruction. We also present specially designed data structures that allow an efficient implementation of Saber key-encapsulation mechanism, utilizing the dot-product instruction to speed-up the polynomial convolution. The proposed FrodoKEM implementation achieves $4.37\times $ higher throughput than the state-of-the-art implementation on a V100 GPU. This paper also presents the first implementation of Saber on GPU platforms, achieving 124,418, 120,463, and 31,658 key exchanges per second on RTX3080, V100, and T4 GPUs, respectively. Since matrix-multiplication and polynomial convolution operations are the most time-consuming operations in lattice-based cryptographic schemes, we strongly believe that the proposed methods can be beneficial to other KEM and signatures schemes based on lattices. [ABSTRACT FROM AUTHOR]

In this work, we present a fast and area-efficient software-hardware implementation of the supersingular isogeny key encapsulation (SIKE) mechanism. Our software-hardware design achieves both the flexibility of software as well as the efficient performance of intense computations of hardware. In particular, our implementation takes advantage of new and highly optimized hardware modules for addition, multiplication, and hardware-software control, targeted at Xilinx FPGAs. In conjunction with a small RISC-V processor, we can support all four SIKE parameter sets. On a Virtex-7 FPGA, this implementation occupies 3,492 slices, 78 DSPs, and 29 BRAMs, to perform encapsulation and decapsulation over SIKEp434, SIKEp503, SIKEp610, and SIKEp751 in 14.5, 19.2, 29.8, and 42.7 ms, respectively. Despite supporting all four parameter sets, this design has the best area-time product of all isogeny accelerators in the literature. [ABSTRACT FROM AUTHOR]

We discuss a stochastic algorithm to design tuning controllers for cryptographic True Random Number Generators, compliant to NIST recommendations, as an effective low-complexity solution to counteract entropy variability in integrated architectures implementing tunable entropy sources. Taking as a reference the min-entropy concept, we discussed the proposal from both the theoretical and hardware design points of view, validating claims with proofs and experiments. Depending on the target accuracy, the proposed architecture is scalable, and its profitable use in TRNG design strongly depends on the kind of core entropy sources taken into account. Furthermore, we show that the low-complexity entropy measurement techniques exploited in this proposal can be used to design a legitimate alternative to the Adaptive Proportion Health Test recommended in the NIST 800.90B publication. [ABSTRACT FROM AUTHOR]

This paper presents a full hardware implementation of the eXtended Merkle Signature Scheme (XMSS), a NIST approved and IETF RFC specified post-quantum cryptography (PQC) algorithm. An optimized node traversal is proposed to enable efficient memory utilization without compromising the computational latency of the L-tree and Merkle tree construction, which are two key components used for the compression of the Winternitz One-Time Signature (WOTS) public key in XMSS. The computation of the authentication path during signature generation has also been significantly sped up by our proposed hardware implementation of the Buchmann, Dahmen, and Schneider (BDS) algorithm. Our implementation has completely avoided the use of block random-access memory, which is known to be vulnerable to side-channel attacks. The memory requirement has been highly optimized for implementation with small flip-flop chains and register counters as pointers for fast data access. To the best of our knowledge, this is the first full hardware implementation of all three key generation, signing and verification operations of XMSS. The design has been prototyped and evaluated on a 28 nm FPGA platform to demonstrate its performance improvements over the most efficient software and hardware/software co-design methods reported to date. Specifically, it increases the computational efficiency of the best reported XMSS implementation for key generation and signature generation by about 20% and 50%, respectively. It can also run at 10% higher clock speed than the fastest hardware implementation of signature verification in FPGA with 8% lower hardware resource utilization. [ABSTRACT FROM AUTHOR]

The Supersingular Isogeny Key Encapsulation mechanism (SIKE) is the only post-quantum key encapsulation protocol based on elliptic curves and isogeny maps between them. Despite the quantum security of the protocol, SIKE requires a greater number of clock cycles and hence does not provide competitive timing and energy consumption results. However, it is more attractive offering the smallest public key as well as ciphertext sizes, which considering the impact of the communication costs and storage of the keys could become a good fit for resource-constrained devices. In this work, we present the fastest practical implementation of SIKE, targeting the platform Cortex-M4 based on the ARMv7-M architecture. We performed our measurements on the STM32F407VG microcontroller for benchmarking the clock cycles and on Nucleo-F411RE attached to X-NUCLEO-LPM01A (Power Shield) for measuring the energy consumption of the protocol. The low-level finite field arithmetic operations play main role in determining the efficiency of SIKE. Therefore, we mainly focus on their optimization and apply them to all NIST-required security levels. Our SIKEp434 implementation for NIST security level 1 is about 22.97% faster than the counterparts appeared in Seo et al. (2020), where for the SIKEp503, SIKEp610 and SIKEp751 the speedup reaches 21.10%, 19.21% and 19.08%. Finally, we benchmark energy consumption and report optimization of up to 11.9% depending on the NIST security level implementation. [ABSTRACT FROM AUTHOR]

Montgomery reduction is a well-known optimization technique for modular reduction over prime fields. However, it has rarely been used for national institute of standards and technology (NIST) prime fields, because the special structure of NIST primes enables fast reduction that requires fewer computations than Montgomery reduction. In this study, we rediscover the Montgomery reduction for NIST primes and propose a new modular reduction method by applying partial modular reduction to Montgomery reduction. Using this new modular reduction method and other optimization techniques, such as pipelining and parallel processing, we propose an efficient elliptic curve cryptography (ECC) coprocessor over NIST prime fields. The implementation results indicate that the proposed coprocessor can perform one elliptic curve point multiplication in 0.055 ms with only 194.7 k gate counts. This is a considerably higher speed per area compared to previous research. [ABSTRACT FROM AUTHOR]

Cryptographic co-processors are integral to the modern System-on-Chips. Flexibility in such designs serves dual purpose, i.e., it enables acceleration of different essential cryptographic primitives (Encryption/Authentication/Pseudo Random Number Generation (PRNG)) and also results in design compaction via resource sharing. In this context, a novel resource-shared crypto-coprocessor, named AE$HA-3 is presented, which combines two National Institute of Standards and Technology (NIST) standardized algorithms, i.e., Advance Encryption Standard (AES) and Secure Hash Algorithm-3 (SHA-3). Due to algorithmic dissimilarities, so far no resource-shared implementation enabling AES key scheduling/ enc/dec and SHA-3 has been presented. AE$HA-3 exploits resource-sharing for area reduction, i.e., integration of Look-Up-Tables (I-Tables) for AES enc/dec; logical optimization of Six Input Equation (SixIE) for SHA-3; a Unified XOR Section to carry out both key whitening in AES and SHA-3 transformations. Furthermore, the AES key scheduling was performed using the same resource-shared hardware. The proposed AE$HA-3 on Xilinx Virtex FPGA family results in highest hardware efficiency in terms of Throughput per Slice (TPS), along with a 49.37% area consumption reduction, when compared against the smallest stand-alone implementations presented to date. [ABSTRACT FROM AUTHOR]

In this work, we present a fast parallel architecture to perform supersingular isogeny key encapsulation (SIKE). We propose and implement a fast isogeny accelerator architecture that uses fast and parallelized isogeny formulas. On top of our isogeny accelerator, we build a novel architecture for the SIKE primitive, which provides both quantum and IND-CCA security. We synthesized this architecture on the Xilinx Artix-7, Virtex-7, and Kintex UltraScale+ FPGA families. Over Virtex-7 FPGA’s, our constant-time implementations are roughly 14% faster than the state-of-the-art with a better area-time product. At the NIST security level 5 on a Kintex UltraScale+ FPGA, we can execute the entire SIKE protocol in 15.3 ms. This work continues to improve the speed of isogeny-based computations and also features all parameter sets of the SIKE round 2 specification, with results applicable to NIST’s post-quantum standardization process. [ABSTRACT FROM AUTHOR]

Neural machine translation (NMT) heavily relies on context vectors generated by an attention network to predict target words. In practice, we observe that the context vectors for different target words are quite similar to one another and translations with such nondiscriminatory context vectors tend to be degenerative. We ascribe this similarity to the invariant source representations that lack dynamics across decoding steps. In this article, we propose a novel gated recurrent unit (GRU)-gated attention model (GAtt) for NMT. By updating the source representations with the previous decoder state via a GRU, GAtt enables translation-sensitive source representations that then contribute to discriminative context vectors. We further propose a variant of GAtt by swapping the input order of the source representations and the previous decoder state to the GRU. Experiments on the NIST Chinese–English, WMT14 English–German, and WMT17 English–German translation tasks show that the two GAtt models achieve significant improvements over the vanilla attention-based NMT. Further analyses on the attention weights and context vectors demonstrate the effectiveness of GAtt in enhancing the discriminating capacity of representations and handling the challenging issue of overtranslation. [ABSTRACT FROM AUTHOR]

In this work, we present the first highly-optimized implementation of Supersingular Isogeny Key Encapsulation (SIKE) submitted to NIST’s second round of post quantum standardization process, on 64-bit ARMv8 processors. To the best of our knowledge, this work is the first optimized implementation of SIKE round 2 on 64-bit ARM over SIKEp434 and SIKEp610. The proposed library is explicitly optimized for these two security levels and provides constant-time implementation of the SIKE mechanism on ARMv8-powered embedded devices. We adapt different optimization techniques to reduce the total number of underlying arithmetic operations on the field level. In particular, benchmark results on embedded processors equipped with ARM Cortex-A55@1.766GHz and ARM Cortex-A75@2.803GHz show that the entire SIKE round 2 Key Encapsulation Mechanism (KEM) takes only 98.6 ms and 85.3ms at NIST’s security level 1, respectively. We also evaluated the compressed version of NIST’s security level 1, which requires 134.7 ms and 113.7 ms for Cortex-A55 and Cortex-A75, respectively. Considering SIKE’s extremely small key size in comparison to other post-quantum cryptography candidates, our result implies that SIKE is one of the promising candidates for key encapsulation mechanism on embedded devices in the quantum era. [ABSTRACT FROM AUTHOR]

The elliptic curve cryptography (ECC) has gained attention mainly due to its lower complexity compared to other asymmetric methods while providing the same security level. The most performance critical operation in ECC is the point multiplication. Thus, its efficient implementation is desirable. One of the most secure and lightweight ECC curves, which satisfies all standard security criteria, is the Curve25519. In this paper, a low latency Karatsuba-Ofman-based field multiplier (KOM) and an efficient point multiplication over Curve25519 have been proposed. The improvements have been achieved mainly due to the proposed low latency pipelined KOM and efficient scheduling of field operations. Moreover, an enhanced architecture exploiting a number of well-known differential power analysis (DPA) countermeasures have been implemented. To evaluate this work against the previous ones, FPGA has been exploited to implement the point multiplication architectures. The FPGA implementation results of the enhanced and regular architectures show at least 64% and 33% improvement in AsT ($slice\_{}count \times time$) compared to those in the previous work, respectively. However, AdT ($DSP\_{}count \times time$) metrics in both architectures seem to be similar to the previous work. Furthermore, the time complexity of both enhanced and regular architectures decreases 89% using Zynq-7020. [ABSTRACT FROM AUTHOR]

Pseudorandom bit generator (PRBG) is an essential component for securing data during transmission and storage in various cryptography applications. Among popular existing PRBG methods such as linear feedback shift register (LFSR), linear congruential generator (LCG), coupled LCG (CLCG), and dual-coupled LCG (dual-CLCG), the latter proves to be more secure. This method relies on the inequality comparisons that lead to generating pseudorandom bit at a non-uniform time interval. Hence, a new architecture of the existing dual-CLCG method is developed that generates pseudo-random bit at uniform clock rate. However, this architecture experiences several drawbacks such as excessive memory usage and high-initial clock latency, and fails to achieve the maximum length sequence. Therefore, a new PRBG method called as “modified dual-CLCG” and its very large-scale integration (VLSI) architecture are proposed in this paper to mitigate the aforesaid problems. The novel contribution of the proposed PRBG method is to generate pseudorandom bit at uniform clock rate with one initial clock delay and minimum hardware complexity. Moreover, the proposed PRBG method passes all the 15 benchmark tests of NIST standard and achieves the maximal period of $2^{n}$. The proposed architecture is implemented using Verilog-HDL and prototyped on the commercially available FPGA device. [ABSTRACT FROM AUTHOR]

In this paper, a high-speed elliptic curve cryptography (ECC) processor specialized for primes recommended by the National Institute of Standards and Technology (NIST) was constructed. Toom–Cook multiplication without division was proposed to implement modular multiplication for NIST primes. Compared with a traditional algorithm, the computation complexity was reduced from 16 base multiplications to 7 in 4-way Toom–Cook multiplication. Moreover, we introduced non-least-positive (NLP) form into our design, so that the carry chain in the large array accumulation was broken down, which greatly shortened the critical path and made parallel processing possible. In order to support NLP form and lazy reduction strategy, conventional fast reduction methods for NIST primes were also modified. In addition, pipeline technique at the level of point multiplication was used, so the latency of modular inverse can be covered. Implemented on the Xilinx Virtex-6 FPGA platform, the ECC processor can perform a point multiplication every 54 $\mu s$ at the cost of 30.3k LUTs and 48 DSPs. Synthesized with 180nm CMOS technology, the speed achieves 43.7 $\mu s$ with 466k gate counts. These experimental results show a significantly better performance per area than previous works. [ABSTRACT FROM AUTHOR]

Highlights • Periodic properties of the skew tent map under fixed-point precision constrains. • Limitations of the skew tent map, coupled skew tent map and cross-coupled skew tent maps as PRNG under fixed-point precision constrains. • Developed a new scheme for extracting random binary sequence with the least possible fixed-point fraction length. • FPGA implementation of the proposed scheme. Abstract The random-like behavior of chaotic systems make them perfect candidates for the core of numerous pseudo-random number generators. The coupling of two or more chaotic maps has been proven to increase the random property robustness of the generated sequences. However, these properties are also strongly influenced by the datatype implementation of these generators owing to the effect of the sensitivity to initial conditions. Hence, several factors must be considered concerning the hardware implementation of these coupled chaotic map-based generators. This paper first examines the effect of fixed-point precision implementation on the periodicity of a single skew tent map and the extension of this effect on the statistical properties of the generated sequence from coupled skew tent maps. Then, the effect on cross-coupled skew tent maps is discussed. Further, a modification to the cross-coupled scheme is presented; this achieves a reduction in the fixed-point fraction length required for generating a sequence suitable for cryptographic applications while expanding the dependency on the control parameters of the maps. The generated sequences from the proposed modification met all the applied statistical and correlation test requirements, demonstrating that they possess acceptable random properties and are suitable for cryptographic applications. [ABSTRACT FROM AUTHOR]

States such as Arizona, New York, and Texas are using their own funds to attract semiconductor companies to open manufacturing plants in the United States. This comes after Congress passed the CHIPS and Science Act, which allocated billions of dollars for the construction of new facilities and research into chip technologies. The decline in domestic chip production, from 40% in 1990 to 12% last year, has prompted states to take action. While federal funding is available, it may not be enough to compete with other countries like China. States like New York have created programs to improve companies' chances of receiving federal funding, while Texas has established a task force and provided grants to attract semiconductor businesses. Arizona has also invested in creating facilities and developing a skilled workforce. The goal is to form strong partnerships between companies and higher education institutions to advance semiconductor technology. [Extracted from the article]

Systolic finite field multiplier over $\textit {GF}(2^{m})$ based on the National Institute of Standards and Technology (NIST) recommended pentanomials or trinomials can be used as a critical component in many cryptosystems. In this paper, for the first time, we propose a novel low-complexity unified (hybrid field size) systolic multiplier for NIST pentanomials and trinomials over $\textit {GF}(2^{m})$. We have proposed a computation-core-based design strategy to obtain the desired low-complexity unified multiplier for both NIST pentanomials and trinomials. The proposed multiplier can swift between pentanomial-based and trinomial-based multipliers through a control signal. First of all, a novel strategy is briefly introduced to implement a certain matrix-vector multiplication, which can be packed as a standard computation core (or computation core like). Then, based on the computation-core concept, a novel unified multiplication algorithm is derived that it can realize both the pentanomial-based and trinomial-based multiplications. After that, an efficient systolic structure is presented that it can fully employ the introduced computation core. A detailed example of the proposed unified multiplier (for $\textit {GF}(2^{163})$ and $\textit {GF}(2^{233})$ ) is also presented. Both the theoretical and field-programmable gate array implementation results show that the proposed design has efficient performance in area-time-power complexities, e.g., the proposed design (the one performs $\textit {GF}(2^{163})$ and $\textit {GF}(2^{233})$ multiplications) is found to have at least 14.2% and 13.3% less area-delay product and power-delay product than the combination of the existing individual $\textit {GF}(2^{163})$ and $\textit {GF}(2^{233})$ multipliers (best among all competing designs), respectively. Because of its structural regularity and functional flexibility, the proposed unified multiplier can be used as an intellectual property core for various cryptosystems. [ABSTRACT FROM AUTHOR]

Security has been one of the important problems in the processing, storage and transmission of information. The transfer of information to virtual environments with technological developments has made it necessary to examine the concept of security with different dimensions. Data security can be achieved to a great extent by using randomly generated unpredictable bit sequences in encryption. In this study, approximately 1,000,000 random bits were generated for use in computer science. The Mode2(x) method and the unpredictable nature of chaotic systems are used for random number generation. With this hybrid structure used in the study, it is aimed to gain a different perspective to future studies. However, it is known that the sensitivity of chaotic systems to initial conditions is very high. The most important contribution of the study to the literature is that the initial conditions were determined using optimization algorithms. In this study, Particle Swarm Optimization (PSO) and Ant Colony Optimization (ACO) were used to calculate the initial conditions. To the authors' knowledge, this is the first study to use optimization to determine initial conditions for continuous-time chaotic systems. NIST SP 800-22 Statistical Test Suite was used to analyze the reliability of the generated random bits. It was seen that the proposed method passed all statistical tests successfully (100 %). Histogram and floating frequency analysis were used for the analysis of random numbers obtained from the generated bits. Histogram plots showed uniform distribution. It is seen that there is a homogeneous distribution in the sliding frequency analysis. • Chaotic systems are an effective study area for cryptographic RNG. • Determining the optimal system parameters of the chaotic system is a critical design problem. • This design problem for RNGs is an NP problem. • Optimization algorithms have been used to solve this problem. • The success of the generator has been analyzed through extensive testing. [ABSTRACT FROM AUTHOR]

Systolic implementation of Karatsuba algo- rithm (KA)-based digit-serial multiplier over GF(2^m) on field- programmable gate array (FPGA) platforms has many attractive features, such as efficient tradeoff in area-time complexity and high-throughput rate. But on the other side, it suffers from high register-complexity, which leads to increase in area and power consumption. In this paper, we present an algorithm and architecture for efficient FPGA implementation of KA-based digit-serial systolic multiplier over GF(2^m) based on the National Institute of Standards and Technology (NIST) recommended polynomials. A number of efficient techniques have been explored and used to realize efficient implementation of these multipliers. First, we propose a novel KA-based approach, where the computational complexity is significantly reduced compared with the existing one. Second, we propose efficient register minimization techniques, such as redundant register removal, two-stage pipelining, and register sharing to reduce the register complexity of the proposed structure. Third, we adopt an efficient FPGA-specific digit-parallel implementation strategy to optimize the area-time–power complexities of the proposed structure on FPGA platforms. The results obtained from FPGA synthesis indicate that the proposed multiplier (for field based on NIST trinomial GF(2^233) ) has significantly lower area–time–power complexities than the existing designs, e.g., the proposed structure could achieve 65.7% and 73.6% reduction on area-delay product and power-delay product over the best of existing KA-based systolic structures, respectively. [ABSTRACT FROM AUTHOR]

Eugene Song, another expert speaker at [ABSTRACT FROM AUTHOR]

The US Department of Commerce will soon announce its first funding opportunity for semiconductor companies under the $52 billion CHIPS Act and has urged all companies across the supply chain to sub [ABSTRACT FROM AUTHOR]

NIST has signed a cooperative agreement with Google to develop and produce chips for researchers to be used in making nanotech and semiconductor devices. [ABSTRACT FROM AUTHOR]

Recently, finite field multipliers having high-throughput rate and low-latency have gained great attention in emerging cryptographic systems, but such multipliers over GF(2^m) for National Institute Standard Technology (NIST) pentanomials are not so abundant. In this paper, we present two pairs of low-latency and high-throughput bit-parallel and digit-serial systolic multipliers based on NIST pentanomials. We propose a novel decomposition technique to realize the multiplication by several parallel arrays in a 2-dimensional (2-D) systolic structure (BP-I) with a critical-path of 2TX, where TX is the propagation delay of an XOR gate. The parallel arrays in 2-D systolic structure are then projected along vertical direction to obtain a digit-serial structure (DS-I) with the same critical-path. For high-throughput applications, we present another pair of bit-parallel (BP-II) and digit-serial (DS-II) structures based on a novel modular reduction technique, where the critical-path is reduced to (TA+TX), TA being the propagation delay of an AND gate. A strategy for data sharing between a pair of processing elements (PEs) of adjacent systolic arrays has been proposed to reduce area-complexity of BP-I and BP-II further. From synthesis results, it is shown that the proposed multipliers have significantly lower latency and higher throughput than the existing designs. To the best of authors' knowledge, this is the first report on low-latency systolic multipliers for finite fields where latency is independent of field-order. [ABSTRACT FROM AUTHOR]

The article focuses on the need for institutions and businesses to develop and launch cybersecurity plans to secure their intellectual assets. Topics covered include how technologies change the way businesses collect, save and view company-critical informational assets. Also mentioned is the improving popularity of employees' remote access to their work.

The article discusses the initiatives adopted by the U.S. government to address the issue of cyber security and mentions the role of the insurance industry in the cyber security issue.

The supply chain faces risks on various fronts--including from cyberattacks--imperiling chip and electronic components inventories. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, a new stream key generator Hybrid Discrete Continuous Chaotic System (HDCCS) based on continuous and discrete chaotic systems is proposed. Our solution provides an easy and robust chaos synchronization while decrease the degradation due to finite precision during a digital implementation. Real-time application to wireless speech encryption effectively hides the original signal. Statistical security analysis for the proposed cryptosystem against cryptanalysis attacks, from a strict cryptographic viewpoint, are presented. These results verify and prove that the proposed speech cryptosystem is highly secure and has a very powerful diffusion and confusion mechanisms widely used in conventional cryptography. [Copyright &y& Elsevier]

Researchers say their new optomechanical accelerometer could be used to calibrate other such devices [ABSTRACT FROM AUTHOR]

Twenty-four herbal dietary supplement powder and extract reference standards provided by the National Institute of Standards and Technology (NIST) were investigated using three different commercially available DNA extraction kits to evaluate DNA availability for downstream nucleotide-based applications. The material included samples of Camellia, Citrus, Ephedra, Ginkgo, Hypericum, Serenoa, and Vaccinium. Protocols from Qiagen, MoBio, and Phytopure were used to isolate and purify DNA from the NIST standards. The resulting DNA concentration was quantified using SYBR Green fluorometry. Each of the 24 samples yielded DNA, though the concentration of DNA from each approach was notably different. The Phytopure method consistently yielded more DNA. The average yield ratio was 22 : 3 : 1 (ng/�L; Phytopure : Qiagen : MoBio). Amplification of the internal transcribed spacer II region using PCR was ultimately successful in 22 of the 24 samples. Direct sequencing chromatograms of the amplified material suggested that most of the samples were comprised of mixtures. However, the sequencing chromatograms of 12 of the 24 samples were sufficient to confirm the identity of the target material. The successful extraction, amplification, and sequencing of DNA from these herbal dietary supplement extracts and powders supports a continued effort to explore nucleotide sequence−based tools for the authentication and identification of plants in dietary supplements. [ABSTRACT FROM AUTHOR]

With medical supplies in short supply, U.S. manufacturers are ready to step in. But it will take more than just flipping a switch. [ABSTRACT FROM AUTHOR]

The idea of growing tissue in the lab to help humans restore lost organs or limbs has generated research on a number of fronts. For their part, scientists at the National Institute of Standards and Technology (NIST) are developing a new kind of light-based sensor to study tissue growth in the lab. [ABSTRACT FROM AUTHOR]

NEWS ANALYSIS: New legislation, if adopted, would set purchasing requirements for government IoT devices, which in turn would affect the availability of secure IoT for industry. [ABSTRACT FROM AUTHOR]

NIST Risk Management Framework 2.0 updates cyber-security policy, and Skype adds live captioning and subtitles for improved accessibility. [ABSTRACT FROM AUTHOR]

The final version of the NIST Risk Management Framework 2.0 is now available, providing government agencies and commercial enterprises alike with new guidance that aligns risk, privacy and cyber-security controls. [ABSTRACT FROM AUTHOR]

NEWS ANALYSIS: The National Institute of Standards and Technology has published a guide to help companies to securely convert their networked factory floor production machinery to wireless. [ABSTRACT FROM AUTHOR]

The article offers information on the Spectrum Access System (SAS) for 3.5 GHz telecom spectrum management from Google, which was demonstrated at the International Symposium on Advanced Radio Technologies (ISART) 2015 held in Boulder, Colorado in May 2015.

The article reports that the U.S. National Institute of Standards and Technology (NIST) is looking to seek help from the manufacturing firms for the development of a tool for deploying wireless network. It mentions that the test bed will be used for the evaluation of network models and simulations at NIST. It highlights that NIST has collected data at a transmission assembly plant which is run by an U.S. automaker.

Perseus Telecom has today announced the deployment of its High Precision Time solution in CoreSite's Northern Virginia market. [ABSTRACT FROM AUTHOR]

The article offers information on the need of public and private sectors to combine their efforts for the growth of internet of things (IoT) according to the Federal Mobile Computing Summit. Topics discussed include views of Gray Brooks, senior application program interface (API) strategist for the General Service Administration, addressing the IoT security issues not met completely by cybersecurity discussions, and the federal government interested in opening its data through API.

The article offers information on a framework that is launched by the National Institute of Standards and Technology in February 2014, to help companies improve their cybersecurity. Topics discussed include the requirement for companies to identify sensitive information and develop procedures for its protection, advice for an investor to determine the defense of a prospective investment against breach of data and analysis of industry practices against cyberattacks.

The article the utility of National Institute of Standards and Technology's (NIST) Framework for Improving Critical Infrastructure Cybersecurity in helping organizations to secure information security program. Further it discusses the Graham-Leach-Bliley Act which compels financial institutions to protect sensitive customer information. It informs that the Framework is based upon the Safeguard information security risk management factors.

The article focuses on the demand for hardware security for mobile devices. It discusses the three component system of hardware-rooted mobile security which includes roots of trust (RoTs), an application programming interface and a policy enforcement engine. It mentions a forecast on the need of hardware security by market analysis firm Allied Business Intelligence Inc. (ABI), and implementing computer security in mobiles devices by computer industry.

Once a year, three officials bearing three separate keys meet at the bottom of a stairwell at the International Bureau of Weights and Measures, in Sevres, France. There they unlock a vault to check that a plum-size cylinder of platinum iridium alloy is exactly where it should be. Then they close the vault and leave the cylinder to sit alone, under three concentric bell jars, as it has for most of the past 125 years. [ABSTRACT FROM PUBLISHER]