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MOS N-path mixer-first receivers are capable of providing instantly-reconfigurable RF impedance and bandwidth while achieving moderate noise figure (NF) and high linearity, but their frequency tuning range is limited by both LO (local oscillator) generation and the RF port input capacitance. State-of-the-art mm-wave MOS N-path receivers often compromise performance to cover the mm-wave range, but this paper presents the theory and design considerations for a new topology of N-path mixer which makes use of high fT HBTs and breaks this trade-off between performance and tuning range. Here, we borrow from a previously derived LTI model for MOS-based N-path mixers to derive an analogous model for the HBT-based counterpart which provides a meaningful comparison between the performance of the two topologies. We show that the HBT-based implementation is capable of operation beyond the frequency limits of MOS-based implementations while maintaining comparable NF and linearity without consuming exorbitant power. Measurements done on a proof-of-concept chip in GlobalFoundries BiCMOS8HP are consistent with our models and simulations. By organizing process parameters and user-selected design variables into dimensionless ratios, we provide expressions for key performance metrics which enable the designer to make informed decisions about trade-offs and optimizations for both LO generation and the mixer core. [ABSTRACT FROM AUTHOR]

This paper investigates various important microwave characteristics of an independently biased 3-stack InGaP/GaAs heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) chip at both small-signal and large-signal operation. By taking the advantage of the independently biased functionality, bias condition for individual transistor can be adjusted flexibly, resulting in the ability of independent control for both small-signal and large-signal performances. It was found that at small-signal operation stability and isolation characteristics of the proposed configuration can be significantly improved by controlling bias condition of the second-stage and the third-stage transistors while at large-signal operation its linearity and power gain can be improved through controlling the bias condition of the first-stage and the third-stage transistors. To demonstrate the benefits of using such an independently biased configuration, a measured optimum large-signal performance at an operation frequency of 1.6 GHz under an optimum bias condition for the high gain, low distortion were obtained as: \text PAE = 23.5\,\,\% , \text P\text {out}= 12 dBm; \text Gain= 32.6 dB at IMD3 = −35 dBc. Moreover, to demonstrate the superior advantage of the proposed configuration, its small-signal and large-signal performance were also compared to that of a single stage common-emitter, a conventional 2-stack, an independently biased 2-stack and a conventional 3-stack configuration. The compared results showed that the independently biased 3-stack is the best candidate among the configurations for various wireless communications applications. [ABSTRACT FROM AUTHOR]

Adder structures utilizing SiGe Hetero-junction Bipolar Transistor (HBT) digital circuits are examined for use in high clock rate digital applications requiring high-speed integer arithmetic. A 4-gate deep test structure for 32-bit addition using a 210 GHz fT process has been experimentally verified to operate with 37.5 ps delay or 26.7 GHz speed. The paper documents a unique blend of CML and ECL circuit innovations, which is needed to obtain this result. The chip is estimated to have a power-delay product of 109 ps-W at a device temperature of 85^\circ~\C. A low power design is shown to have a power-delay product of 48 ps-W at 21.7 GHz. Speed-power trade-offs are explored through pure ECL logic and varying current. Additionally, with next generation SiGe HBTs, this work shows that 40 GHz is achievable at slightly above room temperature. [ABSTRACT FROM PUBLISHER]

In this paper we present a novel computational method for calculating the heterojunction bipolar transistor (HBT) physical characteristics in the time domain. To calculate the HBT high frequency properties, the Gummel–Poon equivalent circuit model is applied to replace the HBT in the circuit and a set of governing ordinary differential equations (ODEs) is formulated. We directly decouple the system ODEs and solve each decoupled ODE with the monotone iterative method in the time domain. This solution methodology proposed here has been applied to semiconductor device simulation by us earlier, and we find this method for the HBT simulation has good accuracy and converges globally. Compared with the HSPICE circuit simulator results, our results present the accuracy, efficiency, and robustness of the method. [Copyright &y& Elsevier]