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The article discusses the implementation of confidential container groups on Microsoft Azure, with particular emphasis given to experiments involving three configurations including Base, SNP, and Parma. The Parma architecture is described and security invariant discussed. Additional topics covered include cloud computing, utility virtual machines (UVMs), data integrity and security, and encryption key.

Steve Jobs, co-founder of Apple, left the company in 1985 with the intention of creating a powerful computer for the education sector. He formed a new company called NeXT and took five Apple employees with him. NeXT aimed to create a computer that would meet the specific needs of higher education and research institutions. Despite facing financial challenges and criticism, NeXT made significant contributions to computing, including the development of the NeXTSTEP operating system, which later became the foundation for Apple's Mac operating system. Ultimately, Apple acquired NeXT in 1996, bringing Jobs back to the company and solidifying NeXT's impact on the industry. [Extracted from the article]

The article focuses on the evolution of digital technology and its impact on test equipment, highlighting the historical significance of the Jacquard loom and von Neumann architecture in shaping modern computing.

Ada Lovelace, known as the world's first computer programmer, played a crucial role in the development of the first general-purpose computer. Lovelace's annotations on a paper about the analytical engine, designed by Charles Babbage, showcased her technical expertise and philosophical insights. She recognized the potential of computers to go beyond mathematical calculations and discussed concepts such as programmability and artificial intelligence. Despite never seeing a computer in action, Lovelace's visionary ideas laid the foundation for modern computing. Unfortunately, Babbage's analytical engine was never built due to lack of funding. [Extracted from the article]

This article discusses the difficulties encountered with multicore processors which are used to increase the clock speed of microprocessors but can act in asynchronous and unpredictable ways. One approach to address this is linearizability which is the de facto correctness condition to reason about safety properties in concurrent programming but only deals with sequential specifications.

The article offers an introduction and overview of another article in the issue on the subject of the relationship between computer vulnerabilities and computer science theory. The author suggests that in the past, what he calls "exploits," or ways to get a computer system to behave contrary to its creators' intent, were seen as ad hoc, but that now it is clear that such vulnerabilities are inherent in the overall structure of computing.

The article explores how deep learning models have evolved from relying on hand-crafted operator libraries to utilizing compiler-based approaches for optimization, especially with the growing diversity of hardware platforms. It highlights the Apache TVM project, which allows machine learning engineers to compile models for specific hardware targets, optimizing performance without altering model accuracy. The article points to an accompanying paper that proposes a unified transformation approach that optimizes model architectures through program transformations, avoiding expensive retraining and achieving significant performance gains without compromising accuracy.

This article reviews the development of virtual memory and its impact on the computing industry. Topics include the discovery of virtual memory including the Atlas architecture, operating system, and programming language that led to it as well as its impact on overall computer memory, multi-programming and secure computing.

The article looks at mentoring in the computer science fields of programming languages and computer architecture. The authors outline two volunteer-based multi-institution mentoring programs they were involved in creating, SIGPLAN-M and Computer Architecture Long-term Mentoring (CALM). Topics include how the programs recruit mentors and match them with mentees; how mentees say they have benefited from their relationships with mentors; and challenges they faced in setting up and administering the programs.

The article discusses SYNERGY, a software-centric approach to field-programmable gate array (FPGA) virtualization in data centers. This approach addresses performance and power challenges by enabling features like task suspension, resumption, migration, and process isolation. Unlike traditional hardware-centric methods, SYNERGY rewrites Verilog hardware description code to work with a Verilog JIT compiler, allowing for higher-level state management and task handling. While it incurs significant overhead and requires further development to match current software virtualization performance, SYNERGY's innovative perspective could lead to improved FPGA architecture and reduced overhead in the future.

The article calls for an emphasis on static analysis in the design of software development tools to detect and prevent anomalies, security risks, and nonfunctional code. Legal ramifications for safeguarding source code are outlined along with the alleged increasing complexity of software engineering and diversity of computer programming languages. The author calls for standardization of software engineering methods and computer architecture along with an increased emphasis on human-computer interaction.

Research shows that companies that are investing heavily in digital technologies to harness the power of human-machine collaboration are dramatically improving their bottom lines. But it takes people to conceive of and manage the innovations, and the authors are convinced that success in the future depends on a human-centered approach to artificial intelligence (AI). In this article they present their IDEAS framework, which calls for attention to five elements of the emerging technology landscape: intelligence, data, expertise, architecture, and strategy. The authors discuss each of these in turn, examining how companies such as McDonald’s, Etsy, and the online grocer Ocado have implemented human-driven AI processes and applications to become leading players in their industries. If you’re eager to transform your own business, the IDEAS frame- work can help you develop a road map for AI-enabled innovation. [ABSTRACT FROM AUTHOR]

The article discusses various aspects of computer-related linear physical and virtual addresses, and it mentions Cambridge University’s CHERI computer architecture platform and the computer memory-based difficulties that are associated with translating from linear virtual to linear physical addresses. The ARM and x64 types of central processing units (CPUs) are examined, along with object-oriented computing and the Rational R1000/s400 computer.

Speculative execution attacks present an enormous security threat, capable of reading arbitrary program data under malicious speculation, and later exfiltrating that data over microarchitectural covert channels. This paper proposes speculative taint tracking (STT), a high security and high performance hardware mechanism to block these attacks. The main idea is that it is safe to execute and selectively forward the results of speculative instructions that read secrets, as long as we can prove that the forwarded results do not reach potential covert channels. The technical core of the paper is a new abstraction to help identify all microarchitectural covert channels, and an architecture to quickly identify when a covert channel is no longer a threat. We further conduct a detailed formal analysis on the scheme in a companion document. When evaluated on SPEC06 workloads, STT incurs 8.5% or 14.5% performance overhead relative to an insecure machine. [ABSTRACT FROM AUTHOR]

The exposits on the scaling of chatbots to deliver customer service by social welfare providers. Information is offered on the methods by which chatbot architecture was modeled on real-world interactions with service providers as well as background on the customer service experience within existing systems of social welfare. The automation of various types of interactions encountered by seekers of public sector services is described.

The article discusses the generation and sharing of multimedia data produced from cloud-connected and mobile Internet of Things sensing and computing devices. The author proposes a multimedia data retrieval architecture consisting of a multi-hop Ethernet "backbone" and the Internet of Things cloud in an attempt to reduce data delivery delays.

When extremely low-energy processing is required, the choice of data representation makes a tremendous difference. Each representation (e.g., frequency domain, residue coded, and log-scale) embodies a different set of tradeoffs based on the algebraic operations that are either easy or hard to perform in that domain. We demonstrate the potential of a novel form of encoding, race logic, in which information is represented as the delay in the arrival of a signal. Under this encoding, the ways in which signal delays interact and interfere with one another define the operation of the system. Observations of the relative delays (for example, the outcome of races between signals) define the output of the computation. Interestingly, completely standard hardware logic elements can be repurposed to this end and the resulting embedded systems have the potential to be extremely energy efficient. To realize this potential in a practical design, we demonstrate two different approaches to the creation of programmable tree-based ensemble classifiers in an extended set of race logic primitives; we explore the trade-offs inherent to their operation across sensor, hardware architecture, and algorithm; and we compare the resulting designs against traditional state-of-the-art hardware techniques. [ABSTRACT FROM AUTHOR]

Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. Compared to a large monolithic die, an MCM combines many smaller chiplets into a larger system, substantially reducing fabrication and design costs. Current MCMs typically only contain a handful of coarse-grained large chiplets due to the high area, performance, and energy overheads associated with inter-chiplet communication. This work investigates and quantifies the costs and benefits of using MCMs with finegrained chiplets for deep learning inference, an application domain with large compute and on-chip storage requirements. To evaluate the approach, we architected, implemented, fabricated, and tested Simba, a 36-chiplet prototype MCM system for deep-learning inference. Each chiplet achieves 4 TOPS peak performance, and the 36-chiplet MCM package achieves up to 128 TOPS and up to 6.1 TOPS/W. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. To mitigate inter-chiplet communication overheads, we introduce three tiling optimizations that improve data locality. These optimizations achieve up to 16% speedup compared to the baseline layer mapping. Our evaluation shows that Simba can process 1988 images/s running ResNet-50 with a batch size of one, delivering an inference latency of 0.50 ms. [ABSTRACT FROM AUTHOR]

The article discusses changes in computer science from what is referred to a computation-centric model to data-centric, and the importance of adapting thinking patterns in order to drive technological innovation. It examines the looming end of Moore's Law as related to computer chip design and memory access. The article expounds upon computational thinking, historical thinking, data-centric thinking, and architectural thinking.

The article discusses the computer software development framework known as microservice architecture (MSA). It examines how MSA challenges software development organizations (SDOs) during legacy code migration, and provides tips for adapting legacy code to MSA.

The Steve Jobs Archive has released a new online exhibit featuring a video of Steve Jobs' presentation at the 1983 International Design Conference. In the video, a 28-year-old Jobs discusses the history of computers and predicts that they will become the predominant medium of communication in the future. He also talks about the potential uses of computers in education, financial transactions, and software development. The exhibit includes additional footage of Jobs discussing topics such as design simplicity and the future of personal computers. The exhibit can be accessed for free on the Steve Jobs Archive website. [Extracted from the article]

The article discusses the views of computer science scholar John von Neumann as pertaining to the work of scholar Alan Turing's 1936 paper entitled "On Computable Numbers, With an Application to the Entscheidungsproblem." According to the article, von Neumann urged computer builders to concern themselves with practical limits rather than theoretical limits. The article also discusses the work of mathematician Calvin Mooers.

The authors discuss the need for a new branch of computer science to develop accelerator-level parallelism in both computer hardware and software. They mention various forms of parallel processing that already exist, present a case study of mobile systems on a chip that are starting to rely on accelerator-level parallelism, and examine how the science might proceed in the future.

The article focuses on Application Programming Interfaces (API) which are services that enable one software or application to use features or services of another application, platform, or device. Topics include the industry adoption of APIs, the driving factors behind API management, and the value of open source APIs in modern organizations; and outlines the building blocks of an open source API and API management principles, including simplicity, flexibility, transformability, and reusability.

The author discusses the hourglass model of computer architecture. He mentions the use of such a model in the design of the internet and its protocols or operating systems like Unix, the significance of the intermediary spanning layer, and presents a formal model of layering to create the spanning layer.

The IBM researchers have demonstrated how the new chip can run a common image-recognition AI 22 times as fast as any commercial chip on the market, and more efficiently, beating even the latest chips from NVIDIA, the leading manufacturer of those used for AI. However, NorthPole's design, which is specialised for running already trained AI models, means it can't perform other tasks, such as actually training an AI, or running larger AI models that require more memory than is available on the chip. A COMPUTER chip inspired by the human brain can run artificial intelligence image-recognition operations 22 times as fast as comparable commercial chips. [Extracted from the article]

The article discusses concern among computer designers and computer scientists regarding the conclusion of the observation known as Moore's Law. It also discusses the concept of circuit cleverness, 3D (three-dimensional) integration, and the term Turing tariff."

FEATURES The top ten programming languages Software analyst TIOBE (tiobe.com) compiles a monthly ranking of programming languages, based on web traffic. 1 Python 17.2% 2 C 15.1% 3 Java 12% 4 C++ 10.8% 5 C 4.3% 6 Visual Basic 4.1% 7 JavaScript 2.8% 8 Assembly language 2.2% 9 SQL 1.8% 10 PHP 1.7% 1 Python The TIOBE index makes Python the most popular programming language in the world - or at least, the one people want to know about more than any other. Here are a few that are worth checking out: codecademy.com khanacademy.org codeavengers.com udacity.com Programming vs scripting Languages such as Python and JavaScript are sometimes referred to as scripting languages, rather than programming languages. BELOW Scratch is a great tool for youngsters to learn programming basics DIAGRAM: Top 10 programming languages DIAGRAM: Top 10 programming languages DIAGRAM: Top 10 programming languages. [Extracted from the article]

A recent study from Tianjin University of Technology in China introduces a new high-performance heterogeneous hardware architecture for Brain-Computer Interface (BCI) systems. By combining ARM and FPGA technologies, the system achieves a 93.3% classification accuracy for EEG signals with minimal time delay and power consumption. The research highlights the practicality and significance of this novel BCI architecture, offering potential advancements in human-computer interaction. [Extracted from the article]

The Lenovo Tech World 2024 conference in Seattle brought together top CEOs like Jensen Huang, Satya Nadella, and Mark Zuckerberg to focus on harnessing AI. The event highlighted Intel CEO Pat Gelsinger's announcement of an alliance to shape the future of x86 architecture, uniting rivals like Intel and AMD. The focus on Hybrid AI and partnerships across the tech industry underscored the importance of collaboration in navigating the impact of AI on hardware and software industries. [Extracted from the article]

Intel and Advanced Micro Devices (AMD) have joined forces to address the increasing competition from Arm Holdings by establishing a group to ensure software compatibility across their chips. While x86 architecture has been dominant in laptops, PCs, and data centers for 40 years, Arm's licensing model has allowed it to gain market share. The new advisory group, which includes companies like Broadcom and Oracle, aims to make AMD and Intel chips consistent and compatible across various applications. Intel's CEO emphasized the adaptability of x86 technology for future innovations like AI in laptops, highlighting the resilience and growth potential of the ecosystem. [Extracted from the article]

This article looks at error control in quantum computing. Quantum error correction, or error correction in quantum computing, needs to be able to account for errors occurring in the final state changes in quantum circuits. Due to the way qubits, quantum bits, work they are susceptible to unwanted changes in state making the error rate in quantum computing unacceptably high. Topics include a discussion of quantum gates and how they can be protected in error control, magic-process distillation, and necessary advances in quantum computing architecture to support quantum error correction.

We propose a method called Node Replication (NR) to implement any concurrent data structure. The method takes a single-threaded implementation of a data structure and automatically transforms it into a concurrent (thread-safe) implementation. The result is designed to work well with and harness the power of modern servers, which are complex Non-Uniform Memory Access (NUMA) machines with many processor sockets and subtle performance characteristics. Using NR requires no expertise in concurrent data structure design, and the result is free of concurrency bugs. NR represents a paradigm shift of how concurrent algorithms are developed: rather than designing for a data structure, we design for the architecture. [ABSTRACT FROM AUTHOR]

The article discusses the use of formally verified software to protect an autonomous helicopter against cyber attacks. Topics include the testing of vehicles by the U.S. Defense Advanced Research Projects Agency (DARPA) through its High-Assurance Cyber Military Systems (HACMS) program, the role of a trusted computing base (TCB) in computer architecture for security, and the componentization of systems.

The article presents a methodology to benchmark beyond-complementary metal oxide semiconductors (CMOS) devices at an architectural level while improving performance-scaling trends as computer architects adopt multi-core architectures to maintain processor performance scaling through parallel processing.

The article discusses research on the design of microprocessors to prevent cyberattacks. Topics include the significance of computer architecture for hacking, the role of memory buffers in computer chips in hardware vulnerability, and designs of computer chips that prevent malicious software from operating on the hardware.

Model compression is crucial for the deployment of neural networks on devices with limited computational and memory resources. Many different methods show comparable accuracy of the compressed model and similar compression rates. However, the majority of the compression methods are based on heuristics and offer no worst case guarantees on the tradeoff between the compression rate and the approximation error for an arbitrarily new sample. We propose the first efficient structured pruning algorithm with a provable tradeoff between its compression rate and the approximation error for any future test sample. Our method is based on the coreset framework, and it approximates the output of a layer of neurons/filters by a coreset of neurons/filters in the previous layer and discards the rest. We apply this framework in a layer-by-layer fashion from the bottom to the top. Unlike previous works, our coreset is data-independent, meaning that it provably guarantees the accuracy of the function for any input $x\in \mathbb {R}^{d}$ , including an adversarial one. [ABSTRACT FROM AUTHOR]

It is challenging to bridge the performance gap between binary convolutional neural network (BCNN) and floating-point CNN (FCNN). This performance gap is mainly caused by the inferior modeling capability and training strategy of BCNN, which leads to substantial residuals in intermediate feature maps between BCNN and FCNN. To minimize the performance gap, we enforce BCNN to produce similar intermediate feature maps with the ones of FCNN. This intuition leads to a more effective training strategy for BCNN, i.e., optimizing each binary convolutional block with blockwise distillation loss derived from FCNN. The goal of minimizing the residuals in intermediate feature maps also motivates us to update the binary convolutional block architecture to facilitate the optimization of blockwise distillation loss. Specifically, a lightweight shortcut branch is inserted into each binary convolutional block to complement residuals at each block. Benefited from its squeeze-and-interaction (SI) structure, this shortcut branch introduces a fraction of parameters, e.g., less than 10% overheads, but effectively boosts the modeling capability of binary convolution blocks in BCNN. Extensive experiments on ImageNet demonstrate the superior performance of our method in both classification efficiency and accuracy, e.g., BCNN trained with our methods achieves the accuracy of 60.45% on ImageNet, better than many state-of-the-art ones. [ABSTRACT FROM AUTHOR]

One of the significant tasks in remaining useful life (RUL) prediction is to find a good health indicator (HI) that can effectively represent the degradation process of a system. However, it is difficult for traditional data-driven methods to construct accurate HIs due to their incomprehensive consideration of temporal dependencies within the monitoring data, especially for aeroengines working under nonstationary operating conditions (OCs). Aiming at this problem, this article develops a novel unsupervised deep neural network, the so-called times series memory auto-encoder with sequentially updated reconstructions (SUR-TSMAE) to improve the accuracy of extracted HIs, which directly takes the multidimensional time series as input to simultaneously achieve feature extraction from both feature-dimension and time-dimension. Further, to make full use of the temporal dependencies, a novel long-short time memory with sequentially updated reconstructions (SUR-LSTM), which uses the errors not only from the current memory cell but also from subsequent memory cells to update the output layer’s weight of the current memory cell, is developed to act as the reconstructed layer in the SUR-TSMAE. The use of SUR-LSTM can help the SUR-TSMAE rapidly reconstruct the input time series with higher precision. Experimental results on a public dataset demonstrate the outstanding performance of SUR-TSMAE in comparison with some existing methods. [ABSTRACT FROM AUTHOR]

Deep neural networks include millions of learnable parameters, making their deployment over resource-constrained devices problematic. Sensitivity-based regularization of neurons (SeReNe) is a method for learning sparse topologies with a structure, exploiting neural sensitivity as a regularizer. We define the sensitivity of a neuron as the variation of the network output with respect to the variation of the activity of the neuron. The lower the sensitivity of a neuron, the less the network output is perturbed if the neuron output changes. By including the neuron sensitivity in the cost function as a regularization term, we are able to prune neurons with low sensitivity. As entire neurons are pruned rather than single parameters, practical network footprint reduction becomes possible. Our experimental results on multiple network architectures and datasets yield competitive compression ratios with respect to state-of-the-art references. [ABSTRACT FROM AUTHOR]

Neural architecture search (NAS) is gaining more and more attention in recent years because of its flexibility and remarkable capability to reduce the burden of neural network design. To achieve better performance, however, the searching process usually costs massive computations that might not be affordable for researchers and practitioners. Although recent attempts have employed ensemble learning methods to mitigate the enormous computational cost, however, they neglect a key property of ensemble methods, namely diversity, which leads to collecting more similar subarchitectures with potential redundancy in the final design. To tackle this problem, we propose a pruning method for NAS ensembles called “ subarchitecture ensemble pruning in neural architecture search (SAEP).” It targets to leverage diversity and to achieve subensemble architectures at a smaller size with comparable performance to ensemble architectures that are not pruned. Three possible solutions are proposed to decide which subarchitectures to prune during the searching process. Experimental results exhibit the effectiveness of the proposed method by largely reducing the number of subarchitectures without degrading the performance. [ABSTRACT FROM AUTHOR]

Popular network pruning algorithms reduce redundant information by optimizing hand-crafted models, and may cause suboptimal performance and long time in selecting filters. We innovatively introduce adaptive exemplar filters to simplify the algorithm design, resulting in an automatic and efficient pruning approach called EPruner. Inspired by the face recognition community, we use a message-passing algorithm Affinity Propagation on the weight matrices to obtain an adaptive number of exemplars, which then act as the preserved filters. EPruner breaks the dependence on the training data in determining the “important” filters and allows the CPU implementation in seconds, an order of magnitude faster than GPU-based SOTAs. Moreover, we show that the weights of exemplars provide a better initialization for the fine-tuning. On VGGNet-16, EPruner achieves a 76.34%-FLOPs reduction by removing 88.80% parameters, with 0.06% accuracy improvement on CIFAR-10. In ResNet-152, EPruner achieves a 65.12%-FLOPs reduction by removing 64.18% parameters, with only 0.71% top-5 accuracy loss on ILSVRC-2012. Our code is available at https://github.com/lmbxmu/EPruner. [ABSTRACT FROM AUTHOR]

Hyperspectral images (HSIs) are of crucial importance in order to better understand features from a large number of spectral channels. Restricted by its inner imaging mechanism, the spatial resolution is often limited for HSIs. To alleviate this issue, in this work, we propose a simple and efficient architecture of deep convolutional neural networks to fuse a low-resolution HSI (LR-HSI) and a high-resolution multispectral image (HR-MSI), yielding a high-resolution HSI (HR-HSI). The network is designed to preserve both spatial and spectral information thanks to a new architecture based on: 1) the use of the LR-HSI at the HR-MSI’s scale to get an output with satisfied spectral preservation and 2) the application of the attention and pixelShuffle modules to extract information, aiming to output high-quality spatial details. Finally, a plain mean squared error loss function is used to measure the performance during the training. Extensive experiments demonstrate that the proposed network architecture achieves the best performance (both qualitatively and quantitatively) compared with recent state-of-the-art HSI super-resolution approaches. Moreover, other significant advantages can be pointed out by the use of the proposed approach, such as a better network generalization ability, a limited computational burden, and the robustness with respect to the number of training samples. Please find the source code and pretrained models from https://liangjiandeng.github.io/Projects_Res/HSRnet_2021tnnls.html. [ABSTRACT FROM AUTHOR]

This paper presents a novel static digital pre-distortion (DPD) method for a current-steering digital-to-analog converter (CS-DAC). The proposed method utilizes the knowledge of the current cell array architecture to calculate the static mismatch currents of the cells. The mismatch values are stored in memory and added to the original input code to generate the new pre-distorted input word. The converter corrects the static error with its own current cells without incorporating an additional calibration DAC (CALDAC) or programmable current sources. This results in a reduction in area, power and simulation run times because of the simpler circuit design. An Overflow-Cell-Selection (OCS) is introduced as a novel solution to further enhance the static linearity of the converter. It also can be implemented as a software solution for already existing DAC designs which do not have an integrated DPD and lab/measurement equipment (e.g., arbitrary wave generator (AWG)). This poses as a strong differentiation factor compared to other state-of-the-art static DPD methods. The evaluation of the proposed DPD is done via simulations in MATLAB and on- chip measurements with a 14-bit CS-DAC in 16 nm. Single tone measurements show a performance gain of the total harmonic distortion (THD) of 12 dB. [ABSTRACT FROM AUTHOR]

In-memory computing using emerging technologies such as Resistive Random-Access Memory (ReRAM) has been proposed as a promising substitute for future computing applications to address the ‘von Neumann bottleneck’. Multiplication is the key component for inner product computation in every digital signal processing (DSP) application and the complexity of multipliers increases greatly with bit-width. Distributed arithmetic (DA) using look-up tables and adder-shifter module has been proposed for inner product computation to achieve multiplier-less efficient DSP architectures, particularly when one of the vectors is a constant and known in advance. Due to the memory wall, DA can be made furthermore latency and energy-efficient when implemented ‘in memory’. In this work, for the first time, we propose two design techniques to compute inner product completely in memory using DA. This is accomplished by storing the precomputed look-up table contents in a ReRAM array and implementing adder-shifter module also in the same array. The adder-shifter is implemented in memory using majority gates which are in turn realized as READ operations in the memory array. Two methods of mapping: latency-optimized and area-optimized and their comparison in terms of latency and area are presented. The proposed method-1 achieves $\approx 60$ % energy savings compared to CMOS and the proposed method-2 achieves 10.59 times higher throughput compared to CMOS. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive design space exploration for boosting energy efficiency of a fast Fourier transform (FFT) VLSI accelerator, exploiting several approximate multipliers (AxM) combined with approximate adder (AxA) circuits. The FFT hardware herein presented consists of a fixed-point sequential architecture using a radix-2 butterfly with decimation in time. We explore a set of AxMs – namely Dynamic Range Unbiased (DRUM), Rounding-based Approximate (RoBA), leading one Bit-based Approximate (LoBA), and Truncated approach – jointly with the LOA, ETA-I, CopyA, CopyB, Trunc0, Trunc1 approximate adders. The approximate arithmetic operators are used in the butterfly kernel with exploration of the approximation levels (for the ${L}$ and ${K}$ least-significant bits, respectively, for the AxM and AxA), aiming at discovering the most energy-efficient configuration under a design-time QoR constraint. The mean square error and peak signal-to-noise ratio metrics define which approximate levels combining ${L}$ and ${K}$ variations will enable the FFT to process signals to generate spectrograms without significant losses. Our results show that the LoBA multiplier with $L$ =8 together with the LOA, Trunc1 and Trunc0, at different approximation levels, provide most energy savings with controllable quality degradation, presenting a minimum decrease of 20.2% in power dissipation without degrading the spectrogram generation quality. [ABSTRACT FROM AUTHOR]

Single-electron transistors (SETs) exhibit a unique characteristic of Coulomb oscillation which can find many digital applications with area efficiency. More specifically, both MOS and SET devices can be used to implement XOR gates with almost the same area costs regardless of the number of their inputs, outperforming pure CMOS solutions. As multiple-input XOR gates are abundant in the finite field polynomial multiplication which represents the most frequent computation in elliptic curve cryptosystem, hybrid SET-MOS technology can substantially reduce the area cost for this application. This paper presents polynomial multiplication architectures with hybrid SET-MOS transistors and explores Karatsuba-algorithm based multiplication for further area optimization. Simulations show that the proposed hybrid SET-MOS implementations can typically provide around 37% savings in terms of gate count compared to their traditional CMOS counterparts. [ABSTRACT FROM AUTHOR]

Computing in memory (CIM) is a promising candidate for high throughput and energy-efficient data-driven applications, which mitigates the well-known memory bottleneck in Von Neumann architecture. In this paper, we present a reconfigurable bit-serial operation using toggle spin-orbit torque magnetic random access memory (TSOT-MRAM) to perform the computation completely in the bit-cell array instead of in a peripheral circuit. This bit-serial CIM (BSCIM) scheme achieves higher throughput and energy efficiency in CIM. First, basic Boolean logic operations are realized by utilizing the feature of TSOT device. A bit-cell array that implements the bit-serial operation is then built to provide the communication between column and row necessary for arithmetic operations, such as the carry propagation of addition and multiplication. Finally, we analyze the reliability of BSCIM scheme and demonstrate the performance advantage by performing convolution operations for $28\times 28$ handwritten digit images in a BSCIM architecture. The results show that the delay and energy of BSCIM architecture are respectively reduced by 1.16-5.49 times and 1.12-1.43 times compared with the existing digital CIM architectures. Besides, its throughput and energy efficiency are also enhanced to 51.2 GOPS and 9.9 TOPS/W respectively. [ABSTRACT FROM AUTHOR]

As an important and challenging problem, multidomain learning (MDL) typically seeks a set of effective lightweight domain-specific adapter modules plugged into a common domain-agnostic network. Usually, existing ways of adapter plugging and structure design are handcrafted and fixed for all domains before model learning, resulting in learning inflexibility and computational intensiveness. With this motivation, we propose to learn a data-driven adapter plugging strategy with neural architecture search (NAS), which automatically determines where to plug for those adapter modules. Furthermore, we propose an NAS-adapter module for adapter structure design in an NAS-driven learning scheme, which automatically discovers effective adapter module structures for different domains. Experimental results demonstrate the effectiveness of our MDL model against existing approaches under the conditions of comparable performance. [ABSTRACT FROM AUTHOR]

The staggering innovations and emergence of numerous deep learning (DL) applications have forced researchers to reconsider hardware architecture to accommodate fast and efficient application-specific computations. Applications, such as object detection, image recognition, speech translation, as well as music synthesis and image generation, can be performed with high accuracy at the expense of substantial computational resources using DL. Furthermore, the desire to adopt Industry 4.0 and smart technologies within the Internet of Things infrastructure has initiated several studies to enable on-chip DL capabilities for resource-constrained devices. Specialized DL processors reduce dependence on cloud servers, improve privacy, lessen latency, and mitigate bandwidth congestion. As we reach the limits of shrinking transistors, researchers are exploring various application-specific hardware architectures to meet the performance and efficiency requirements for DL tasks. Over the past few years, several software optimizations and hardware innovations have been proposed to efficiently perform these computations. In this article, we review several DL accelerators, as well as technologies with emerging devices, to highlight their architectural features in application-specific integrated circuit (IC) and field-programmable gate array (FPGA) platforms. Finally, the design considerations for DL hardware in portable applications have been discussed, along with some deductions about the future trends and potential research directions to innovate DL accelerator architectures further. By compiling this review, we expect to help aspiring researchers widen their knowledge in custom hardware architectures for DL. [ABSTRACT FROM AUTHOR]