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Integrated microspectrometers implemented in silicon photonic chips have gathered a great interest for diverse applications such as biological analysis, environmental monitoring, and remote sensing. These applications often demand high spectral resolution, broad operational bandwidth, and large optical throughput. Spatial heterodyne Fourier-transform (SHFT) spectrometers have been proposed to overcome the limited optical throughput of dispersive and speckle-based on-chip spectrometers. However, state-of-the-art SHFT spectrometers in near-infrared achieve large optical throughput only within a narrow operational bandwidth. Here we demonstrate for the first time, to the best of our knowledge, a broadband silicon nitride SHFT spectrometer with the largest light collecting multiaperture input (320×410µm^2) ever implemented in an SHFT on-chip spectrometer. The device was fabricated using 248 nm deep-ultraviolet lithography, exhibiting over 13 dB of optical throughput improvement compared to a single-aperture device. The measured resolution varies between 29 and 49 pm within the 1260–1600 nm wavelength range.

Surface grating couplers are fundamental building blocks for coupling the light between optical fibers and integrated photonic devices. However, the operational bandwidth of conventional grating couplers is intrinsically limited by their wavelength-dependent radiation angle. The few dual-band grating couplers that have been experimentally demonstrated exhibit low coupling efficiencies and rely on complex fabrication processes. Here we demonstrate for the first time, to the best of our knowledge, the realization of an efficient dual-band grating coupler fabricated using 193 nm deep-ultraviolet lithography for 10 Gbit symmetric passive optical networks. The footprint of the device is 17×10µm^2. We measured coupling efficiencies of −4.9 and −5.2dB with a 3-dB bandwidth of 27 and 56 nm at the wavelengths of 1270 and 1577 nm, corresponding to the upstream and downstream channels, respectively.

Silicon nitride (SiN) waveguides provide a substantially lower index contrast, thermo-optic coefficient, and reduced birefringence compared to silicon-on-insulator waveguides. These properties make SiN a prominent candidate for implementation of ultra-wideband dual-polarization photonics circuits with a great potential for datacom applications. State-of-the-art SiN power splitters are still hampered in terms of either bandwidth or single-polarization operation. Here, we propose to overcome these limitations by exploiting modal and waveguide symmetry engineering in a single-mode slot waveguide. This topology prevents mode-beating, while granting symmetric power splitting for both polarizations. Experimental characterization of the fabricated device shows low loss ($ {\lt} {0.62}\,\,{\rm dB}$<0.62dB) and imbalance ($ {\lt} {0.6}\,\,{\rm dB}$<0.6dB) within an unprecedented bandwidth of 420 nm (1.26–1.68 µm).

Wideband and polarization-independent wavelength filters with low sensitivity to temperature variations have great potential for wavelength division multiplexing applications. However, simultaneously achieving these metrics is challenging for silicon-on-insulator photonics technology. Here, we harness the reduced index contrast and the low thermo-optic coefficient of silicon nitride to demonstrate waveguide Bragg grating filters with wideband apolar rejection and low thermal sensitivity. Filter birefringence is reduced by judicious design of a triangularly shaped lateral corrugation. Based on this approach, we demonstrate silicon nitride Bragg filters with a measured polarization-independent 40 dB optical rejection with negligible off-band excess loss, and a sensitivity to thermal variations below 20 pm/°C.

Novel 3D stacked Gate-All-Around (GAA) nanowires CMOS architectures were developed recently for their very low leakage potentialities and high current drivability for sub-22nm nodes. In this paper, we will discuss some challenges and innovations associated to such devices integration as well as their potential applications.

We present a novel approach to pattern aggressive aspect ratio Si/Si1-xGex superlattices on Silicon On Insulator (SOI) wafers. This approach is based on the anisotropic etching of Si/SiGe superlattices with final dimensions down to 30nm, and the isotropic etching of the SiGe selectively to silicon. This isotropic etching was developed in a remote plasma chamber, and in-situ in an Inductive Coupled Plasma (ICP) reactor.

Novel 3D stacked Gate-All-Around (GAA) nanowires CMOS architectures were developed recently for their very low leakage potentialities and high current drivability for sub-22nm nodes. In this paper, we will discuss some challenges and innovations associated to such devices integration as well as their potential applications.

We present a novel approach to pattern aggressive aspect ratio Si/Si1-xGex superlattices on Silicon On Insulator (SOI) wafers. This approach is based on the anisotropic etching of Si/SiGe superlattices with final dimensions down to 30nm, and the isotropic etching of the SiGe selectively to silicon. This isotropic etching was developed in a remote plasma chamber, and in-situ in an Inductive Coupled Plasma (ICP) reactor.