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Byline: Gaurav. Trivedi, Pushpendra. Singh, Arun. Oinam, Ranjit. Singh Introduction: Linear accelerator (LINAC) embedded with kV source-imager system is capable to do image-guided radiotherapy. The only disadvantage of cone-beam computed [...]

Byline: Gaurav. Trivedi, Arun. Oinam, Budhi. Yadav, Pushpendra. Singh, Ranjit. Singh, Ngangom. Robert Introduction: Total skin electron beam therapy, commonly known as TSET, is a good choice of treatment for [...]

Byline: Shikha. Goyal, Poorva. Vias, Kannan. Periasamy, Renu. Madan, Gaurav. Trivedi, Sudheer. Devana, Himani. Prashar, Divya. Khosla Purpose: We undertook a prospective planning study to describe the delineation of ileal [...]

Myocardial infarction (MI) is a cardiac abnormality in which the coronary artery gets blocked, causing millions of fatalities every year. MI has a very high mortality and disability rate; therefore, with the detection of MI, it is also imperative to determine the location of the blockage to provide on−time treatment to avoid any fatality. In this brief, for the first time, a VLSI architecture is proposed that can determine the location of the infarction in real-time. The proposed architecture classifies the electrocardiogram (ECG) into twelve classes and achieves an average accuracy, sensitivity, and specificity of 99.90%, 99.49%, and 99.94%, respectively. Its area utilization is 1.69 $mm^{2}$ at SCL $180~nm$ Bulk CMOS technology node, and the power consumption is $268.9 ~\mu W$ at 250 KHz. The low area and power requirements and real-time classification capability make the classifier suitable for wearable devices.

Nonvolatile memories, such as resistive random access memory (RRAM), for in-memory computing (IMC), have shown great potential in accelerating neural networks (NNs). However, existing IMC architectures rely on the area and power-hungry analog-to-digital converters (ADCs) for sensing the current, diminishing all the benefits of RRAM. Also, enhancing memory density is essential for implementing compact and efficient artificial intelligence (AI) systems. Implementing multiple states in a single memory cell decreases the resistance between states, making it difficult to sense the current. Thus, incorporating ADCs in multilevel cells (MLCs) further increases the design cost. This article proposes an ADC-less reprogrammable RRAM-based IMC architecture. The ADC-less sensing scheme converts the RRAM array current into its digital equivalent. The proposed scheme can distinguish RRAM resistive states equivalent to 4-bit/cell with a minimal resistance margin of 0.3 $\text{K}\Omega $ between two consecutive states. It is realized with only 12 transistors, the least among the state-of-the-art designs used in IMC architectures. This article also presents an MLC programming method, resulting in a 22% cycle-to-cycle and device-to-device variation-tolerant design with an average power consumption of $21.5 ~\mu \text{W}$ , which is 60.18% less than the contemporary IMC architectures. Furthermore, the proposed current sensor (CS) requires only 12 transistors which is the least among the state-of-the-art works.

Continuous monitoring of the electrical activity of heart signals using wearable Internet of Healthcare Things (IoHTs) devices plays a crucial role in decreasing mortality rates. However, this continuous monitoring using an electrocardiogram (ECG) or vectorcardiogram (VCG) generates huge clinical data. Moreover, these devices are constrained in terms of ON-chip storage, data transmission capacity, and power. Thus, handling a large amount of data is difficult with these devices, making it necessary to compress these data for storage and transmission. Lossless or near-lossless data compression solves this problem, ensuring that no relevant physiological/clinical information is lost in the compression process. Therefore, low-power, resource-efficient, and lossless VLSI architectures are proposed in this article to compress multichannel ECG/VCG data. The designs are tested using the PTB database for both ECG and VCG data and can achieve compression ratios (CRs) of 3.857 and 4.45 with minimal power and area requirements making them suitable for low-power wearable healthcare devices.

Byline: Ranjit. Singh, Arun. Oinam, Gaurav. Trivedi, Harpreet. Kainth, Jangvir. Shahi, Baljinder. Singh, Rakesh. Kapoor Aim: In the present study, surface doses within the target area and contralateral breast (CLB) [...]

Byline: Gaurav. Trivedi, Chandra. Dixit, Arun. Oinam, Rakesh. Kapoor, Amit. Bahl Aim: The aim of the present study was to access the need of daily cone-beam computed tomography (CBCT) and [...]

Lattice-based homomorphic encryption schemes provide strong resistance against quantum and classical computer-based adversary security attacks. In this article, we present a software-hardware co-design of two partially homomorphic encryption (PHE) schemes employing an ARM-System on Chip (ARM-SoC) and an field programmable gate array (FPGA). This provides necessary acceleration to PHE methods in the ecosystem mentioned above. The first PHE scheme is designed for generic homomorphic encryption, while the second scheme is aimed at resource optimized lightweight IoT-driven applications. For seamless assimilation, a robust and reliable low latency data transfer protocol is developed between the FPGA-based accelerator IP and ARM-SoC host system. The proposed PHE schemes are realized using Verilog hardware description language on multiple FPGA platforms. The proposed lightweight scheme is $52.71\times$52.71× more resource-efficient than the pipelined BGV RLWE-based method. It exhibits $1.43\times$1.43× and $1.29\times$1.29× better throughput than non-pipelined and pipelined realizations of the BGV RLWE-based scheme. The proposed hardware accelerators realized on FPGA platforms having lesser clock speed and consuming lower resources showcase significant speedup compared to their software implementations making our proposed method an efficient alternative to enhance security in edge-enabled IoT devices.

Myocardial Infarction (MI) is a critical heart abnormality causing millions of fatalities worldwide every year. MI progress in three stages based on its severity causing several changes in an Electrocardiogram (ECG) signal. It is very critical to capture these variations, which requires continuous monitoring of the ECG signal of the patient. Therefore, it becomes imperative to develop a low power VLSI architecture to address the prognosis of MI. In this brief, for the first time, an area and power efficient design of a five stage classifier is proposed, which detects the progression of various stages of MI using ECG beats in real time. The proposed architecture has an area and total power utilization of $1.38mm^{2}$ and $5.12~\mu W$ , respectively at SCL 180nm Bulk CMOS technology. The low power and area requirements and multiclass classification capability of the proposed design make it suitable to be used in wearable devices.

In this brief, a MOS-based memcapacitor emulator operating at $1.2~MHz$ is proposed. The analytical model of the proposed emulator is verified numerically and experimentally. Numerical analysis of the proposed memcapacitor with respect to various parameters is performed using $Cadence~Virtuoso$ with $TSMC~180~nm$ PDKs followed by post-layout simulation, which also validates its correctness. Its area utilization and power consumption are $2077.85~\mu m^{2}$ and $2.726~mW$ , respectively. Its operating frequency is $1.71\times $ higher than its nearest contemporary memcapacitor. Physical experiments are conducted utilizing $CA3080$ to establish the correctness of the proposed emulator.

In this brief, we propose a Resistive Random Access Memory (RRAM) based self-resetting Integrate and Fire ( $\text{I}\&\text{F}$ ) neuron. The proposed neuron circuit does not require any external bias voltage and the integration of control unit required to reset RRAM into neuron circuit optimizes its overall power consumption. The neuron circuit proposed in this brief consists of two RRAMs for integrate and fire operations, whereas, pulse propogation and reset circuit consists of 22 CMOS transistors. It consumes $1.5~fJ$ per spike, which is 48% and 53% less than the recent neurons designed using, nanoscale FBFET and PDSOI-MOSFET, respectively. The operating frequency of proposed neuron ranges from $277~KHz$ to $03~MHz$ , which is at least 7.5% and 10% higher than the operating frequencies of above mentioned recent neurons, respectively. The inclusion of reset circuit into RRAM based neuron circuit enables the implementation of large scale spiking neural network (SNN), which makes it superior in terms of power and energy consumption.

Modulo polynomial multiplication is an essential mathematical operation in the area of finite field arithmetic. Polynomial functions can be represented as tensors, which can be utilized as basic building blocks for various lattice-based post-quantum cryptography schemes. This paper presents a tensor-based novel modulo multiplication method for multivariate polynomials over $GF(2^{m})$GF(2m) and is realized on the hardware platform (FPGA). The proposed method consumes $6.5\times$6.5× less power and achieves more than $6\times$6× speedup compared to other contemporary single variable polynomial multiplication implementations. Our method is embarrassingly parallel and easily scalable for multivariate polynomials. Polynomial functions of nine variables, where each variable is of degree 128, are tested with the proposed multiplier, and its corresponding area, power, and power-delay-area product (PDAP) are presented. The computational complexity of single variable and multivariate polynomial multiplications are $O(n)$O(n) and $O(np)$O(np), respectively, where $n$n is the maximum degree of a polynomial having $p$p variables. Due to its high speed, low latency, and scalability, the proposed modulo multiplier can be used in a wide range of applications.

The work presented in this article focuses on designing a floating MOS-dynamic threshold voltage MOSFET (DTMOS)-based circuit to emulate a memristor. The proposed circuit consists of four transistors, including a DT-MOSFET and an external capacitor, which helps obtain high-frequency operations up to 3 MHz. This facilitates easier integration of the devices and monolithic IC fabrication. The correctness of the proposed emulator is validated by conducting various parametric analyses at different operating frequencies and process corners, and it generates acceptable pinched hysteresis loops (PHLs) at various frequencies. Furthermore, pre- and post-layout validation of the proposed emulator are also performed using Cadence Virtuoso with Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm process design kits (PDKs) to prove its effectiveness as a memristor. The area and power consumption of the proposed emulator are $157.48~\mu \text {m}^{2}$ and $8.24~\mu \text {W}$ , respectively. The physical experiment of the proposed memristor emulator is performed using ALD $1106~n$ -channel MOSFETs to characterize its functionality as a real-life memristor. It is also used in designing a memristor-based application to showcase its applicability in power and area optimal circuit design.

Atrial fibrillation (AF) is a recurrent and life-threatening disease leading to rapid growth in the mortality rate due to cardiac abnormalities. It is challenging to manually diagnose AF using electrocardiogram (ECG) signals due to complex and varied changes in its characteristics. In this article, for the first time, an end-to-end edge-enabled machine learning-based VLSI architecture is proposed to classify ECG excerpts having AF from normal beats. Researchers have found that abnormal atrial activity is confined to the low-frequency range through the decades. Therefore, in the proposed work, this frequency band is directly analyzed for AF detection, which has not previously been discussed. The proposed architecture is implemented using 180-nm bulk CMOS technology consuming $11.098~\mu {\mathrm{ W}}$ at $25~ {\text {kHz}}$ and exhibits an accuracy of 92.37% for class-oriented classification and 81.60% for subject-oriented classification. The low-power realization of the proposed design, as compared to the state-of-the-art methods, makes it suitable to be used for wearable devices.

In this paper, we propose an optimized meminductor emulator for high frequency operations. For the first time, the proposed meminductor emulator is designed using only MOS transistors making it realizable using monolithic IC fabrication. The numerical analysis of the proposed meminductor is performed employing Cadence Virtuoso with TSMC $180~nm$ PDKs, and its behavior is verified with respect to different parameters, such as voltage, frequency, and process corner variations. Post layout analysis and physical experiments are also conducted to validate the proposed design. It is found that the area utilization and power consumption of the proposed meminductor are $2350.67~\mu m^{2}$ and $3.3~mW$ , respectively. Its maximum operating frequency is $20~MHz$ , and it is $3.42\times $ , $2\times $ , and $258\times $ more efficient in terms of area utilization, maximum operating frequency, and power consumption, respectively, compared to its nearest contemporary meminductors. Further, the applicability of the proposed meminductor is also verified by designing a chaotic oscillator to exhibit its utility in a wide range of applications.

In this manuscript, an optimized MOS-based memcapacitor emulator is proposed using active elements and a resistor. The correctness of the proposed emulator is validated by performing pre and post layout analyses using $Cadence~Virtuoso$ with $TSMC~180~nm$ PDKs. Its area utilization and power consumption are $2034.65~\mu m^{2}$ and $1.86~mW$ , respectively. The maximum operating frequency of the proposed emulator is $24~MHz$ . It is $34\times $ , $4\times $ , and $8.189 \times $ better in terms of operating frequency, area, and power than its nearest contemporary memcapacitor emulator. A physical experiment is conducted to further verify the characteristics of the proposed emulator using $CA3080$ analog ICs. An adaptive learning circuit using the proposed memcapacitor is designed to showcase its effectiveness for practical applications.

ABSTRACTHypergraph partitioning is commonly used in solving very large scale integration (VLSI) placement problem, data mining, sparse matrix multiplication, and parallel computing. This paper presents a novel heuristic for hypergraph partitioning based on nonlinear programming. In our approach we consider adjacent one-dimensional bins. Since the reduction of cuts is equivalent to reducing the net length across the two bins, the vertices are moved across the bins in such a way that the density of vertices in each bin is balanced as per the partitioning requirement and reduction in the wirelength. For the Walshaw partitioning benchmarks, our tool NAPs’ results are consistently comparable to that obtained by Chaco. Our tool NAP produces better cuts than Chaco on 22 instances out of 29 graph samples.

•Experimental performance study of latent heat storage system was investigated.•Erythritol as phase change material and cooking waste oil as working fluid was used.•Thermal performance was enhanced by placing finned heat transferring fluid tubes.•The impact of inlet parameters variation on the melting progress was examined.•Experimental thermal behavior of the system was validated with numerical results.

The challenge of current radiocommunication systems is the efficient use of the frequency spectrum. One of the rapidly evolving tools is a RadCom system, which combines the functionality of a radar sensor with a communication interface. RadCom systems are used in several fields, and the presented work is focused on their applications in the automotive industry. The goal was to design a modulation technique and generate modulation data, which will be suitable for radar determination of the distance and velocity of targets, but also enable their mutual communication. A model of the RadCom system, which simultaneously allows a simulation of detection and communication of several moving targets, has been developed. Herein, a method of generating pseudo-random data based on the MD5 hashing algorithm is described. The proposed method of radar signal processing enables unambiguous detection of moving targets and determination of the position and velocity of these targets. Principles of synchronization and coding of a radar and communication mode of the RadCom system are explained. A numerical verification of the proposed algorithms using simulation tools is discussed in the final part of the work. The proposed system solution achieves more than 70% probability that the decoded message will not contain erroneous bits. [ABSTRACT FROM AUTHOR]