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This letter describes a direct Cu bonding technology to there-dimensionally integrate heterogeneous dielets based on a chip-on-wafer configuration. 100- $\mu \text{m}$ -cubed blue $\mu $ LEDs temporarily adhered on a photosensitive resin are interconnected by semi-additive plating (SAP) without thermal compression bonding. By using SAP bonding, a lot of dielets can be stacked on thin 3D-IC chiplets. The following three key technologies are applied to solve the yield issues of SAP bonding. After pick-and-place assembly, additional coplanarity enhancement eliminates Cu bridges grown to a small gap between the $\mu $ LEDs and photosensitive resin. The $\mu $ LEDs arrays with sidewalls insulated by room-temperature ozone-ethylene-radical (OER)-SiO2-CVD are successfully bonded on sapphire wafers and a thin 3D-IC with through-Si via (TSV). Further design optimization is required, but partial seed pre-etching works well to increase the yield. Fully integrated module implementation with the 3D-ICs will be the next stage, however, we discuss a superior prospect for yield enhancement toward nearly 100%.

This study focuses on enhancing the bendability of flexible interconnects with out-of-plane corrugation for flexible hybrid electronics. We propose two typical configurations of 3D corrugated interconnects: serpentine and trapezoidal. Three methods are introduced to fabricate these corrugated interconnects. The advantages and drawbacks of each fabrication strategy are discussed, and the impact of the 3D corrugation geometry and material on bendability is elucidated. In addition, the material properties of two types of negative photosensitive materials, SU-8 and F-PD (flexible-photoimageable dielectric), are compared. Results show that the resistance increase of 3D corrugated interconnects after a 5 mm radius bending test is drastically lower (by approximately 1900%–2000%) than that of conventional 2D planar interconnects.

ObjectiveA sizeable proportion of patients with secondary mitral regurgitation (SMR) do not receive guideline-directed medical therapy (GDMT) for heart failure (HF). We investigated the association between the use of GDMT and mortality in patients with SMR who underwent transcatheter edge-to-edge repair (TEER).MethodsWe retrospectively analysed patients with SMR and a left ventricular ejection fraction of <50% who underwent TEER at three centres. According to current HF guidelines, GDMT was defined as triple therapy consisting of beta-blockers, renin–angiotensin system (RAS) inhibitors and mineralocorticoid receptor antagonists (MRAs). Patients were divided into two groups: GDMT and non-GDMT groups. We calculated the propensity scores and carried out inverse probability of treatment weighting (IPTW) analyses to compare 2-year mortality between the two groups.ResultsOf 463 patients, 228 (49.2%) were treated with GDMT upon discharge. IPTW-adjusted Kaplan-Meier curve showed patients with GDMT had a lower incidence of mortality than those without GDMT (19.8% vs 31.1%, p=0.011). In IPTW-adjusted Cox proportional hazards analysis, GDMT was associated with a reduced risk of 2-year mortality (HR: 0.58; 95% CI: 0.35 to 0.95; p=0.030), which was consistent among clinical subgroups. Moreover, patients with GDMT had a higher rate of left ventricular reverse remodelling at 1 year after TEER than those without GDMT.ConclusionGDMT, defined as triple therapy consisting of beta-blockers, RAS inhibitors and MRAs, was associated with a reduced risk of 2-year mortality after TEER for SMR. Optimisation of medical therapy is crucial to improve clinical outcomes in patients undergoing TEER for SMR.

Thin‐film polyimides were prepared by solvent‐less vapor deposition polymerization (VDP) from pyromellitic dianhydride and 4,4′‐oxydianiline at 200 °C for liner dielectric formation of vertical interconnects called through‐silicon vias (TSVs) used in three‐dimensionally stacked integrated circuit (3DICs). FTIR, synchrotron XPS, and TDS were employed for determining the imidization ratio, and in addition, the mechanical properties, coefficient of thermal expansion and Young's modulus, of the VDP polyimide were characterized on Si wafers. The VDP polyimide exhibited extremely high conformality, beyond 75%, toward high‐aspect‐ratio deep Si holes, compared with conventional SiO2prepared by plasma‐enhanced chemical vapor deposition. The adhesion between the VDP polyimide and Si wafer was enhanced by an Al‐chelate promotor. Remarkably, the VDP polyimide TSV liner dielectrics showed much less thermomechanical stresses applied to the Si surrounding the TSVs than the plasma‐chemical vapor deposition SiO2. The small keep‐out zone is expected for scaling down highly reliable 3DICs for the upcoming real artificial intelligence society. Through‐silicon vias (TSVs) as 3D interconnects are key components toward threedimensionally stacked integrated circuits (3DICs) to communicate between IC chips in massively parallel at a high speed like the human brain. To solve the thermomechanical stress issue of thin‐film TSV liner dielectrics, vapor‐deposited polymerization (VDP) polyimide formed at 200 °C is characterized on Si wafers. Highly reliable TSVs with the VDP polyimides can be expected for post‐5G applications in real artificial intelligence society in the future.

Catheter-based renal denervation has significantly reduced blood pressure in previous studies. Following a positive pilot trial, the SPYRAL HTN-OFF MED (SPYRAL Pivotal) trial was designed to assess the efficacy of renal denervation in the absence of antihypertensive medications.

Strained-Si technology is crucial to improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs). To introduce large strain into the channel, we proposed a structure for the negative thermal expansion gate electrode. In this study, we used manganese nitride as the gate material, which is a negative thermal expansion material. The fabricated MOSFETs with the manganese nitride gate showed a 10% increase in electron mobility compared to the MOSFET with the Al gate. The results show that the negative thermal expansion gate technology is promising as a technology booster for MOSFET scaling.

We have proposed and developed 3D integration technologies based on self-assembly using surface tension of liquid in this decade. In this paper, microbump bonding and bumpless bonding in face-up and/or face-down configuration are introduced for fine-pitch interconnect formation. In addition, "non-transfer stacking", in other word, flip-chip self-assembly and "transfer stacking" called reconfigure-wafer-to-wafer using SAE carrier are explained.

Glyoxylic acid is seen as a promising candidate to replace formaldehyde as reducing agent in electroless Cu baths. For deposition on ruthenium, the anodic reaction of glyoxylic acid has been evaluated and compared to formaldehyde using linear sweep voltammetry. Significant differences were observed for the deposition of copper on ruthenium. First of all, a faster nucleation to shorten the total process time, was inferred from open-circuit potential measurements. Secondary, we found 2,2' bipyridyl worked as stabilizer, brightener, and suppressor in this glyoxylic acid-based electroless bath. Thirdly, the purity of the copper films improved when 2,2' bipyridyl was present in the solution. Using the optimized composition for the electroless bath, we demonstrate a conformal Cu seed layer deposition (~100 nm) inside high aspect ratio (16.7) through Si vias. This work shows the potential for electroless Cu seeding for a through Si via metallization.

Electroless deposition of Cu was investigated on thin Co layer for through Si via with high aspect ratio structure. The electroless deposition bath was optimized for minimizing Co corrosion during Cu nucleation by using electrochemical analysis. Glyoxylic acid, which is known as non-toxic reducing agent for electroless Cu deposition, showed anodic oxidation on Co, which did not appear for the case of formaldehyde. Furthermore, ratio of complexing agent and Cu ion also impacted Co corrosion; free complexing agent in the electroless deposition bath accelerated corrosion of Co. The optimized electroless bath which contained glyoxylic acid as reducing agent and non-free EDTA performed in 3 um x 50 um TSV, the electroless deposited Cu layer could serve as a seed layer for TSV filling by electrodeposition. The electroless Cu layer was continuously deposited without missing of continuity of Co layer even close to the bottom of TSV.

Abstract

To enable Cu fill of through-Si vias (TSV) with a high aspect ratio (diameter 3 um, depth 50 um), the electroless deposition of a Cu seed on Co liner material was investigated. The reducing agent glyoxylic acid showed anodic oxidation on Co, which did not appear for the case of formaldehyde. From electrochemical analysis, an optimized bath composition caused limited Co corrosion during the electroless Cu nucleation phase. The concentration ratio of the complexing agent (ethylenediaminetetraacetic acid) and copper was found to strongly impact the liner corrosion; in case free complexing agent is present in the bath, the Co corrosion was assisted by complexation and replacement reactions. A continuous seed layer could be deposited in the entire TSV, which enabled the filling by electrochemical deposition (ECD). The substantially thinner total copper overburden generated for this combination of a wet-chemical seed deposition and an ECD fill process contributes to a cost reduction of its chemical mechanical polishing (CMP).

Glyoxylic acid is seen as a promising candidate to replace formaldehyde as reducing agent in electroless Cu baths. For deposition on ruthenium, the anodic reaction of glyoxylic acid has been evaluated and compared to formaldehyde using linear sweep voltammetry. Significant differences were observed for the deposition of copper on ruthenium. First of all, a faster nucleation was inferred from open-circuit potential measurements, which is beneficial as it reduces the total process time. Secondary, we found 2,2' bipyridyl worked as stabilizer and brightener in this glyoxylic acid-based electroless bath. Thirdly, the purity of the copper films improved when 2,2' bipyridyl was present in the solution. Using the optimized composition, we demonstrate a conformal Cu seed layer deposition ([?]100 nm) inside high aspect ratio (16.7) through-Si vias. This work shows the feasibility for electroless Cu seeding in a through-Si via metallization sequence.

Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

A three-dimensional LSI (3D-LSI) that vertically stacks Si chips with a number of through-silicon vias (TSVs) and metal microbumps has attracted much attention recently. However, there are some issues to be resolved in the fabrication of 3D-LSI. In this study, we investigated impacts of local bending stress on the performance of a complementary metal--oxide--semiconductor (CMOS) circuit fabricated in a thinned Si chip. First, we proposed a novel method and a test structure to easily induce the local bending stress in the thinned Si chip. Then, we evaluated the distribution of the local bending stress and its effects on the electrical characteristics of metal--oxide--semiconductor field-effect transistor (MOSFETs). As a result, we observed the degradations of the MOSFET currents and CMOS inverter switching behaviors in accordance with the chip local bending. Our experimental results obviously indicate that the local bending stress caused large fluctuations in the performance of the circuit fabricated in the thinned Si chip.

In this work, high density and small size metal nanodots (MND) with different work-functions were fabricated as a floating gate of nonvolatile memory (NVM) devices by self-assembled nanodot deposition (SAND). The energy band engineering of NVM was demonstrated through controlling MND work-function. For single MND layer floating gate NVM, the retention time was improved by choosing high work-function MND. Furthermore, we proposed a new type NVM with a double stacked MND floating gate. Here, the high work-function MND are placed on the top layer and the low work-function MND are placed on the bottom layer. A large memory window and long retention time were obtained. However, the thermal electron excitation is dominant for the electron discharge process during retention. How to reduce the defects in MND layer is important for further improving of memory characteristics.

We developed a 3D hybrid integration technology of complementary metal oxide semiconductor (CMOS), micro electro mechanical systems (MEMS) and photonic circuits for opto-electronic hetero-integrated systems. The 3D opto-electronic multi-chip module comprising CMOS, MEMS, and photonic devices was fabricated by using 3D hybrid integration technology. The electrical chips of amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS were mounted on the electrical Si interposer with Cu through silicon vias (TSVs). The photonic chips of vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) were embedded into the optical Si interposer with an optical waveguide. The electrical and the optical interposers were precisely bonded together to form 3D opto-electronic multi-chip module. The photonics and electrical devices are communicated via Cu TSVs. The photonic devices were connected via an optical waveguide. Basic functions of CMOS, MEMS and photonic devices in the 3D opto-electronic multi-chip module were successfully evaluated.

A nano-floating gate memory structure with a controllable large threshold voltage window using the Fowler--Nordheim (FN) tunneling program and erasing is proposed. This structure has multiple dot layers composed of a uniform single alloy dot layer in the surrounding silicon dioxide layer and a uniform interoxide layer between these dot layers. Here, we confirmed that multiple alloy FePt nanodot layers provide more charge storage than a single layer, which gives a larger memory window. Thus, multiple nanodot layers can store more charges corresponding to the number of layers with the optimization of several parameters, such as blocking oxide layer thickness. In addition, high operation voltages, low operation speeds due to a thick blocking oxide layer, and the poor retention related to the device structure were revealed, and the improvement of this issue was also discussed. Despite several issues, it is expected that a multiple FePt nanodot memory using FN tunneling will be a candidate structure for a future flash memory because of its larger memory window.

Crystallized W-NDs dispersed in silicon nitride were prepared by self-assembled nanodot deposition (SAND) with extremely high density (1.3x1013/cm2) and small size (1~1.5nm), successfully. XPS results show that the high metallic states of tungsten are remained after 800deg anneal due to the surround silicon nitride. MOS memory capacitor with W-NDs floating gate and HfO2 blocking dielectric was fabricated. A hysteresis memory window of ~ 1.0V is observed under low sweeping gate voltage of {plus minus}5V. A maximum memory window as large as 29V was obtained with sweeping gate voltage of {plus minus}23V, suggesting that it is a good candidate for multi-bit nonvolatile memory application.

Antiperovskite manganese nitride compounds possess the saturation characteristics of the mean free path at an approximate room temperature. Therefore, such compounds show a flat resistance-temperature curve at an approximate room temperature. In this paper, we propose a manganese nitride resistor for high-thermal-stability systems. We fabricated and evaluated the micro/nanoscale manganese nitride compound resistors using the complementary metal-oxide-semiconductor-compatible process. The thermal coefficient of the fabricated manganese nitride compound resistor was as low as that of other near-zero temperature-coefficient of resistivity materials. These results indicate that manganese nitride compounds can achieve higher thermal stability.

The development of poly(3,4-ethylenedioxythiophene) (PEDOT) stimulus electrodes and the relationship between the electrical stimulation of a rabbit retina and electrically evoked potential (EEP) were studied in detail. We fabricated implantable flexible cables with Pt, IrOx, and PEDOT electrodes and evaluated the electrochemical impedances (EIs) and charge injection capacities (CICs) of such electrodes. From the result, we confirmed that PEDOT electrodes have both lower EIs and larger CICs than Pt and IrOxelectrodes. In addition, we performed in vivo experiments with PEDOT electrodes and clarified the relationships between the electrical stimulation of the rabbit retina and EEP. It is highly probable that visual restoration will be realized safely with PEDOT electrodes.

A multilevel charge storage in a multiple FePt alloy nanodot memory is investigated for the first time. It is demonstrated that the memory structure with multiple FePt nanodot layers effectively realizes a multilevel state by the adjustment of gate voltage. Metal oxide semiconductor (MOS) capacitors with four FePt nanodot layers as a floating gate are fabricated to evaluate the multilevel cell characteristic and reliability. Here, the effect of memory window for a nanodot diameter is also investigated, and it is found that a smaller dot size gives a larger window. From the results showing good endurance and retention characteristics for the multilevel states, it is expected that a multiple FePt nanodot memory using Fowler--Nordheim (FN) tunneling can be a candidate structure for the future multilevel NAND flash memory.

Health monitoring and self-management have become increasingly more important because of health awareness improvement, the aging of population, and other reasons. In general, pulse waves are among the most useful physiological signals that can be used to calculate several parameters such as heart rate and blood pressure for health monitoring and self-management. To realize an automatic and real-time pulse-wave monitoring system that can be used in daily life, we have proposed a trans-nail pulse-wave monitoring system that was placed on the fingernail to detect photoplethysmographic (PPG) signals as pulse waves. In this study, we designed a PPG recording circuit that was composed of a 600 x 600 um2 photodiode (PD), an LED driver with pulse wave modulation (PWM) and a low-frequency ring oscillator (RING), and a PPG signal readout circuit. The proposed circuit had a very small area of 2.2 x 1.1 mm2 designed with 0.18 um CMOS technology. The proposed circuit was used to detect pulse waves on the human fingernail in both the reflection and transmission modes. Electrical characteristics of the prototype system were evaluated precisely and PPG waveforms were obtained successfully.

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

We have fabricated various types of Si neural probe for in vivo and in vitro neuronal signal recordings by combining standard photolithography with a bulk micromachining process. To place the probe tip at target areas in the brain precisely, the mechanical properties of the Si neural probes with various tip shapes were carefully investigated under different insertion conditions to brain phantoms. As results, the minimum length and penetration force of the Si neural probe were determined from conditions where the Si neural probe began to penetrate the surface of the brain phantom. To control buckling of the Si neural probe, it is necessary to optimize the insertion rate in accordance with the conditions of the Si neural probe. Although the insertion forces of the Si neural probe with a sharpened tip were smaller than those of the Si neural probe with a normal tip, the effect of the probe tip shape became small with increased insertion speeds.

We studied the effects of postdeposition annealing (PDA) on the films of cobalt nanodots (Co-NDs) dispersed in silica formed by self-assembled nanodot deposition (SAND). High-resolution transmission electron microscopy (HRTEM) analysis showed that the as-grown Co-NDs have a high density of $8\times 10^{12}$/cm2and a small size of ${\sim}1.5$ nm. After PDA at 800 \mbox{\circC}, a monolayer of Co-NDs is produced by agglomeration. Under this PDA condition, the dot size and density are easily controlled by adjusting the thickness of the as-grown Co-ND film. In contrast, a high-temperature PDA of 900 \mbox{\circC} induces the diffusion of cobalt into the silicon substrate and leads to the failure of memory effect. When the PDA temperature is between 600 and 800 \mbox{\circC}, a large counterclockwise hysteresis memory window is obtained. Furthermore, in this region, the charge retention is enhanced by increasing the PDA temperature, which presumably contributes to the release of oxygen from oxidized cobalt.

We have proposed and developed 3D integration technologies based on self-assembly using surface tension of liquid in this decade. In this paper, microbump bonding and bumpless bonding in face-up and/or face-down configuration are introduced for fine-pitch interconnect formation. In addition, “non-transfer stacking”, in other word, flip-chip self-assembly and “transfer stacking” called reconfigure-wafer-to-wafer using SAE carrier are explained.

A three-dimensional stacked IC (3D IC) is a one of the promising structures for enhancing IC performances. A 3D IC consists of several materials such as a Si substrate, metal for through Si via (TSV) and microbump, organic adhesive called the underfill, and so on. These materials generate a coefficient of thermal expansion (CTE) mismatch. On the other hand, heat is generated in the Si substrate during circuit operation and in the environment outside 3D IC, for example. Both the CTE mismatch and heat generation induce local stress caused by expansion of the underfill injected around metal microbumps. In this paper, we report our investigation results of the effects of adhesive expansion on transistor performances by finite element method (FEM) simulation and measurement of transistor characteristics.

As three-dimensional (3D) ICs have many advantages, IC performances can be enhanced without scaling down of transistor size. However, 3D IC has mechanical stresses inside Si substrates owing to its 3D stacking structure, which induces negative effects on transistor performances such as carrier mobility changes. One of the mechanical stresses is local bending stress due to organic adhesive shrinkage among stacked IC chips. In this paper, we have proposed an evaluation method for in-plane local stress distribution in the stacked IC chips using retention time modulation of a dynamic random access memory (DRAM) cell array. We fabricated a test structure composed of a DRAM chip bonded on a Si interposer with dummy Cu/Sn microbumps. As a result, we clarified that the DRAM cell array can precisely evaluate the in-plane local stress distribution in the stacked IC chips.

To enable chronic and stable neural recording, we have been developing an implantable multichannel neural recording system with impedance analysis functions. One of the important things for high-quality neural signal recording is to maintain well interfaces between recording electrodes and tissues. We have proposed an impedance analysis circuit with a very small circuit area, which is implemented in a multichannel neural recording and stimulating system. In this paper, we focused on the design of an impedance analysis circuit configuration and the evaluation of a minimal voltage measurement unit. The proposed circuit has a very small circuit area of 0.23 mm2 designed with 0.18 um CMOS technology and can measure interface impedances between recording electrodes and tissues in ultrawide ranges from 100 O to 10 MO. In addition, we also successfully acquired interface impedances using the proposed circuit in agarose gel experiments.

Glyoxylic acid is seen as a promising candidate to replace formaldehyde as reducing agent in electroless Cu baths. For deposition on ruthenium, the anodic reaction of glyoxylic acid has been evaluated and compared to formaldehyde using linear sweep voltammetry. Significant differences were observed for the deposition of copper on ruthenium. First of all, a faster nucleation to shorten the total process time, was inferred from open-circuit potential measurements. Secondary, we found 2,2’ bipyridyl worked as stabilizer, brightener, and suppressor in this glyoxylic acid-based electroless bath. Thirdly, the purity of the copper films improved when 2,2’ bipyridyl was present in the solution. Using the optimized composition for the electroless bath, we demonstrate a conformal Cu seed layer deposition (~100 nm) inside high aspect ratio (16.7) through Si vias. This work shows the potential for electroless Cu seeding for a through Si via metallization.

Electroless deposition of Cu was investigated on thin Co layer for through Si via with high aspect ratio structure. The electroless deposition bath was optimized for minimizing Co corrosion during Cu nucleation by using electrochemical analysis. Glyoxylic acid, which is known as non-toxic reducing agent for electroless Cu deposition, showed anodic oxidation on Co, which did not appear for the case of formaldehyde. Furthermore, ratio of complexing agent and Cu ion also impacted Co corrosion; free complexing agent in the electroless deposition bath accelerated corrosion of Co. The optimized electroless bath which contained glyoxylic acid as reducing agent and non-free EDTA performed in 3 μm × 50 μm TSV, the electroless deposited Cu layer could serve as a seed layer for TSV filling by electrodeposition. The electroless Cu layer was continuously deposited without missing of continuity of Co layer even close to the bottom of TSV.

To enable Cu fill of through-Si vias (TSV) with a high aspect ratio (diameter 3 μm, depth 50 μm), the electroless deposition of a Cu seed on Co liner material was investigated. The reducing agent glyoxylic acid showed anodic oxidation on Co, which did not appear for the case of formaldehyde. From electrochemical analysis, an optimized bath composition caused limited Co corrosion during the electroless Cu nucleation phase. The concentration ratio of the complexing agent (ethylenediaminetetraacetic acid) and copper was found to strongly impact the liner corrosion; in case free complexing agent is present in the bath, the Co corrosion was assisted by complexation and replacement reactions. A continuous seed layer could be deposited in the entire TSV, which enabled the filling by electrochemical deposition (ECD). The substantially thinner total copper overburden generated for this combination of a wet-chemical seed deposition and an ECD fill process contributes to a cost reduction of its chemical mechanical polishing (CMP).

Glyoxylic acid is seen as a promising candidate to replace formaldehyde as reducing agent in electroless Cu baths. For deposition on ruthenium, the anodic reaction of glyoxylic acid has been evaluated and compared to formaldehyde using linear sweep voltammetry. Significant differences were observed for the deposition of copper on ruthenium. First of all, a faster nucleation was inferred from open-circuit potential measurements, which is beneficial as it reduces the total process time. Secondary, we found 2,2′bipyridyl worked as stabilizer and brightener in this glyoxylic acid-based electroless bath. Thirdly, the purity of the copper films improved when 2,2′bipyridyl was present in the solution. Using the optimized composition, we demonstrate a conformal Cu seed layer deposition (∼100 nm) inside high aspect ratio (16.7) through-Si vias. This work shows the feasibility for electroless Cu seeding in a through-Si via metallization sequence.

Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

To establish liquid-assisted assembly processes applicable to heterogeneous system integrations, we present flip-chip self-assembly of dies with Cu/Sn microbumps using the difference in droplet wetting between hydrophilic and hydrophobic areas. Flip-chip self-assembly is assisted by a water-soluble flux that has high surface tension comparable to that of pure water and contains an additive of a reducing agent for metal oxides. Control of the additive concentration in the flux provides high wettability contrast that enable spontaneous and precise alignment of chips to hydrophilic areas formed on substrates within 5 μm in alignment accuracy. In the subsequent chip bonding process, the reductant can eliminate the metal oxide layer and improve the solder wettability of Sn to the corresponding electrode pads formed on the chips. In addition, we confirm, through electrical characteristic evaluation after thermal compression bonding, that the resulting daisy chain formed between the substrates and self-assembled chips with the flux shows sufficiently low contact resistance of below 20 m$\Omega$/bump without disconnection.

We developed a 3D hybrid integration technology of complementary metal oxide semiconductor (CMOS), micro electro mechanical systems (MEMS) and photonic circuits for opto-electronic hetero-integrated systems. The 3D opto-electronic multi-chip module comprising CMOS, MEMS, and photonic devices was fabricated by using 3D hybrid integration technology. The electrical chips of amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS were mounted on the electrical Si interposer with Cu through silicon vias (TSVs). The photonic chips of vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) were embedded into the optical Si interposer with an optical waveguide. The electrical and the optical interposers were precisely bonded together to form 3D opto-electronic multi-chip module. The photonics and electrical devices are communicated via Cu TSVs. The photonic devices were connected via an optical waveguide. Basic functions of CMOS, MEMS and photonic devices in the 3D opto-electronic multi-chip module were successfully evaluated.

Crystallized W-NDs dispersed in silicon nitride were prepared by self-assembled nanodot deposition (SAND) with extremely high density (1.3x1013/cm2) and small size (1~1.5nm), successfully. XPS results show that the high metallic states of tungsten are remained after 800° anneal due to the surround silicon nitride. MOS memory capacitor with W-NDs floating gate and HfO2 blocking dielectric was fabricated. A hysteresis memory window of ~ 1.0V is observed under low sweeping gate voltage of {plus minus}5V. A maximum memory window as large as 29V was obtained with sweeping gate voltage of {plus minus}23V, suggesting that it is a good candidate for multi-bit nonvolatile memory application.

We derived analytical models for the current-voltage characteristics of double-gate silicon-on-insulator metal-oxide-semiconductor-field-effect-transistors. In the subthreshold region, we derived an analytical subthreshold slope model considering both depleted and induced charges. We proposed a unique definition of threshold voltage of the device, and showed that the threshold voltage is close to the experimentally defined threshold voltage at which the drain current has a specific value. The variation in the surface potential after the threshold voltage was modeled, and hence the models are valid in the moderate-inversion region as well as in the strong-inversion region. The models agree well with experimental data.