Search

We present an MPEG decoder with reduced system costs by employing embedded compression of the reference frames which are used for motion-compensated (MC) decoding. The embedded compression scheme used is based on either block-predictive coding or DCT transform coding, depending on the required memory compression. The compression features simple recovery of (MC) block data, while preventing visible artifacts. The compression was optimized for low costs, enabling real application in a commercial MPEG IC. It was found that the same techniques can be applied in the encoder as well.

A new video processing architecture for high-end TV applications is presented, featuring a flexible heterogeneous multi-processor architecture, executing video tasks in parallel and independently. The signal flow graph and the processors are programmable, enabling an optimal picture quality for different TV display modes. The concept is verified by an experimental chip design. The architecture allows several video streams to be processed and displayed in parallel and in a programmable way, with an individual signal quality. Keywords: TV, multi-window, display processing, co-processor, PiP, scaling, processor architecture.