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Like other technology components of the semiconductor industry, the high-k/metal gate has also continued innovation since its introduction to the 45 nm node. In order to fulfill the ever-increasing power/performance requirements for the future devices, new device architectures are being introduced and the high-k/metal gate should evolve in accordance. In this paper, the development history of the high-k/metal gate stack will be reviewed and the qualities required for the high-k/metal gate stack to match with the future devices will be discussed.

This paper presents systematic studies performed to investigate the properties of dielectric capping layers inserted in high-k metal gate stacks. Physical mechanisms involving such material systems are studied by using identical gate dielectric stacks of La inserted in HfO2 and are studied in both gate-first and gate-last integration. The studies reveal a strong dependence on the thermal budget that the gate stacks are subjected to in forming the capping layer induced dipoles that in turn influences the dipole related threshold voltage shifts and lowered gate leakage. By varying the position of the capping layers in the HfO2 gate dielectric, the threshold voltage and gate leakage are reduced by ~ 200mV and 1.5-2 orders of magnitude respectively in gate-last integration and ~580mV and 4 orders of magnitude respectively in gate-first integration.

We have investigated the electron mobility limited by the remote charge scattering, $\mu_{\text{RCS}}$, in the thin silicon body (${\leq}8$ nm) double-gated metal--oxide--semiconductor field-effect transistors (MOSFETs), focusing on its dependency on the body thickness and the silicon surface orientation. In order to predict the $\mu_{\text{RCS}}$ in such an unprecedented MOSFET system, the adequacy of physical models used in the computation was verified by comparing the computational results with the experimentally determined $\mu_{\text{RCS}}$ from the actual bulk MOSFETs with high-$k$ dielectric fabricated on the (100) and (110) silicon substrates. It has been discovered for the first time that the $\mu_{\text{RCS}}$ is dropped to less than half of the bulk device's $\mu_{\text{RCS}}$ when the body thickness is 5 nm and that the $\mu_{\text{RCS}}$ lowering derived from the body thickness reduction is more serious in the (110)-oriented surface than in the (100)-oriented surface. These mobility trends have been quantitatively explained by the effective mass difference between the two surfaces as well as by the carrier confinement in the metallurgically defined narrow silicon body. These observations indicate the great importance of the systematic reduction of charged traps in high-$k$ gate dielectrics in the advanced devices.

We extensively investigated the physical origin of the threshold voltage $V_{\text{TH}}$ modulation by the Ge channel ion implantation (I/I) in HfO2/TiN/polycrystalline Si gate stack systems. The possible $V_{\text{TH}}$ modulation factors were carefully distinguished from each other by changing the channel dopant concentration and the thickness of the gate dielectric films. It was found that the changes in energy-band offset and dopant concentration in the channel region are minor factors of the $V_{\text{TH}}$ modulation. However, it was also found that $\Delta V_{\text{TH}}$ is sensitive to the oxidation condition of the interfacial oxide layer; a longer oxidation induces a larger $\Delta V_{\text{TH}}$. From the X-ray spectroscopy, we found that a Ge pile-up at the interfacial layer/channel interface occurs, and that the $V_{\text{TH}}$ modulation range correlates well with the amount of piled-up Ge.

A detailed comparison of high-$k$/metal gate stacks fabricated on the (100)- and (110)-oriented substrates has been made. We have verified that there is no structural difference between the gate stacks on the two substrates. The orientation independence of our gate stacks with the high-quality high-$k$/silicon interface for both substrates reveals the intrinsic effects of the crystal orientation on the high-$k$/metal gate devices. This is the first direct evidence that the inversion carrier quantization dependency on the crystal orientations dominates the total gate capacitance in the high-$k$/metal gate system. The analysis of the electron and hole mobilities highlights the fact that the scattering mechanisms inherent in the high-$k$/meta gate stacks limit the mobility enhancement and reduction driven by the effective mass change. No significant difference in the threshold voltage instability under the positive or negative gate bias stress is observed for the two substrates. Therefore, the optimized high-$k$/metal gate stacks enable us to gain certain benefits from the limited modulation of the mobility without sacrificing the stability of the threshold voltage.

FinFET is a promising device candidate for 14nm node CMOS technology. We have developed FinFET device showing superior short channel control at 25nm gate length. This FinFET device featuring gate first high-k/metal gate and merged Epi source/drain process. Key process improvements to resolve the FinFET unique challenges are presented. High drive currents have been obtained for both nFET and pFET. All these results show FinFET is the most promising candidate for 14nm node CMOS technology.

This paper presents the optimization of HfO2 high-k gate dielectrics by utilizing cyclic depositions and anneals during atomic layer deposition (ALD). An order of magnitude reduction in gate leakage is obtained by tuning the anneal temperature, duration and sequence in the ALD. The films are also seen to have three to four times reduction in carbon content. These optimized films are moreover observed to be densified without compromising equivalent oxide thickness (EOT), carrier mobility and threshold voltage. Further electrical characterization supports that there is a suppression of trap assisted tunneling with the optimized ALD process by revealing a stronger temperature dependence on the annealed samples as opposed to the conventional ALD process.

We have previously shown that by varying the position of threshold voltage adjustment cap layers within the gate stack, as well as the oxidant used during processing, it is possible to tune the threshold voltage of n-FET devices, and to concurrently realize a scaling benefit by incorporating group IIA and group IIIB elements into gate dielectrics deposited by metalorganic atomic layer deposition. In this report we have focused on lanthanum oxide cap layers that provide band edge nFET work functions. We compare our previously reported results with ozone oxidation with newly developed processes using oxygen and water as oxidants that result in highly scaled devices with band edge work functions and acceptable leakage characteristics.

In this work, co-sputtered TaC (tantalum + carbon targets + argon) and reactive sputtered TaC (tantalum + methane + argon) were evaluated and compared for application as metal electrodes in high-K/metal gate stacks aimed at 22 nm and beyond technology nodes. The electrical properties of field effect transistors (FETs) were evaluated as a function of TaC deposition conditions and optimized to achieve Tinv scaling. Controlling the deposition conditions as well as the composition of the TaC films was found to be critical to achieve Tinv < 11 Aa.

This paper presents studies performed in engineering high-k metal gate stacks by using capping layers containing Group IIA and IIIB elements. Both high-k gate dielectric (HfO2) and capping materials, namely, the oxides of barium, lanthanum and yttrium are deposited by atomic layer deposition (ALD) to offer superior process control and flexibility. Position specific insertion of cap layers into the gate stack is studied and the device tradeoffs are highlighted. The magnitude of Vt shift is correlated to the electronegativity of the cap layer species and its relative position in the gate stack. For a given cap position, BaO provides the maximum Vt shift, followed by La2O3 and Y2O3 caps. Ozone based ALD processes are shown to adversely impact Tinv scaling due to the re-growth of the interface layer between the high-k and the silicon substrate. Significant improvements in Tinv scaling are obtained by migrating to a water based ALD process.

Ensuring anonymity in sensor networks is a major security goal. Using traffic analysis, the attacker can compromise the network functionality by correlating data flow patterns to event locations/active areas. In this paper we present a novel anonymous communication protocol that hides the location of nodes and obscure the correlation between event zones and data flow from snooping adversaries. We quantify the anonymity strength of our protocol by introducing a new anonymity metric: Degree of Exposure Index. Our protocol is designed to offer flexible tradeoffs between degree of anonymity and communication-delay overhead.

In this paper we will review some of our previous work on ALD deposited high-K dielectric stacks as well as present some of our more recent advances. We have shown that ALD can be used successfully to deposit high quality high-K gate dielectrics of Hf and Zr oxide. In addition, because of the inherent conformality of ALD processes, these dielectrics can be easily migrated to advanced device structures such as FINFETs. We have also been successful in developing ALD processes to deposit rare earth oxides (REOs), such as Y2O3 and La2O3. These processes are useful in creating layered dielectric structures where the REO functions as a threshold voltage adjustment layer. We use physical and electrical characterization of the films as deposited by ALD, including spectroscopic ellipsometry, corona oxide semiconductor charge measurement, TXRF, AES, angle resolved XPS, HRTEM, AFM, MEIS, and RBS, to provide information on the film growth mechanism and the primary parameters that influence the ALD growth of high-K oxides. We further correlate these findings with basic electrical results obtained from MOSFET and MOSCAP devices fabricated using our ALD processes to understand how process changes affect both the as-deposited films as well as the resulting devices.

The criterion for a suitable high-K dielectric/metal gate stack for replacing SiON/Poly-Si stacks in conventional CMOS devices are i) Equivalent oxide thickness (EOT) of {less than or equal to} 1.1 nm, ii) Electron and hole mobilities that are comparable to conventional stacks, and iii) Near Band-Edge (BE) threshold voltages for both nFET and pFET devices. Aggressive scaling and competitive mobilities have been demonstrated using HfO2/metal gate stacks [1] through optimization of interfacial layer composition, choice of suitable metal electrodes and deposition processes, and high thermal budgets that are compatible with conventional FET fabrication. A suitable NFET BE solution compatible with gate first process flow achieved by inserting capping layers containing gp. IIA (e.g., Mg) & gp. IIIB (e.g., La) elements into proven high mobility mid-gap HfO2/TiN gate stacks thereby moving the effective work function (EWF) to nFET BE [2,3]. On the pFET front, the challenge remains that elements with high bulk workfunction exhibit Vt instability as well as inherent scaling limitations after high temperature processing that is required in a gate first process flow.

The requirements for a high-k metal gate n-mosfet solution are that one has a device that exhibits a low Tinv (<1.5 nm), high mobility (~200 @ 1MV/cm) and a threshold voltage in the range of 0-0.2V. While these properties have been independently demonstrated, the key challenge has been to deliver these properties simultaneously and in a gate first , high temperature process flow. We show, that by introducing a new, ultrathin lanthanum oxide dielectric layer in the gate stack, whose function is to provide an electrostatic shift to the onset of threshold these requirements can be acceptably met. This is carried out without compromising gate capacitance and with minimal degradation to the mobility. The underlying physics behind the threshold shift will also be discussed.

Distributed Denial of Service (DDoS) attacks have recently emerged as one of the most potent, if not the greatest, weaknesses of the internet. Previous solutions for this problem try to traceback to the exact origin of the attack by requiring the participation of all routers. For many reasons this requirement is impractical. In the presence of non-participating routers most of the proposed schemes either fail in reconstructing the attack path or end up with an approximate location of the attacker. We propose Scalable Traceback (ST), an approach based on autonomous systems, to address this issue. ST has significant improvements over other works in several dimensions: (1) with just a few tens of packets, ST enables the victim to reconstruct the attack graph, an improvement of two to three orders of magnitude when compared to previous schemes; (2) ST scales to large distributed attacks with thousands of attacks; (3) the reconstruction takes only tens of seconds; (4) ST performs well even in the presence of legacy routers.

In situFourier transform infrared internal reflection spectroscopy (FT-IR/IRS) was used to calculate the adsorption density values for spherical cetyltrimethylammonium bromide (CTAB) micelles at the silica/silicon (SiO2/Si) surface based on a previously developed adsorption density equation. Recent advances in atomic force microscopy (AFM) imaging methodology have led to the ability to image surface micelles, which was not possible previously. These AFM images have been used to independently calculate adsorption density values through offline fast Fourier transform (FFT) analysis. The adsorption density values measured from in situFT-IR/IRS spectra and from AFM images showed good agreement and provide further validation of the FT-IR/IRS adsorption density equation in the low concentration range.

Streaming potential measurements provide valuable information for the validation and interpretation of interfacial phenomena that occur at flat macroscopic surfaces. Planar substrates have been extensively used for the interpretation of events, which occur at particulate surfaces; however, these flat surfaces are often only questionably representative of their particulate counterparts due to variations in surface chemistry and topography. In this study, the zeta potential from planar macroscopic surfaces of PMMA, mica, graphite, fluorite, and calcite have been calculated from streaming potentials measured in aqueous solutions using an asymmetric clamping cell. These zeta potentials have been found to significantly contribute to understanding and interpretation of interfacial phenomena influenced by Coulombic interactions including adsorption, surface forces, and the structure of surface micelles.

The influence of the crystal orientation difference between (100) and (110) silicon substrates on characteristics of La2O3- and Al2O3-capped HfO2dielectric metal--oxide--semiconductor field-effect transistors has been investigated. We observed that the equivalent oxide thickness of the capped devices varies according to the crystal orientation, indicating that the two substrates are not equal in the gate stack scalability within a sub-nanometer regime. We found that the mobility dependency on the crystal orientation is reduced by additional scattering associated with the capping films, suggesting the difficulty to derive maximum benefit from an inherent difference in the mobility depending on the crystal orientation.

Like other technology components of the semiconductor industry, the high-k/metal gate has also continued innovation since its introduction to the 45 nm node. In order to fulfill the ever-increasing power/performance requirements for the future devices, new device architectures are being introduced and the high-k/metal gate should evolve in accordance. In this paper, the development history of the high-k/metal gate stack will be reviewed and the qualities required for the high-k/metal gate stack to match with the future devices will be discussed.

This paper presents systematic studies performed to investigate the properties of dielectric capping layers inserted in high-k metal gate stacks. Physical mechanisms involving such material systems are studied by using identical gate dielectric stacks of La inserted in HfO2 and are studied in both gate-first and gate-last integration. The studies reveal a strong dependence on the thermal budget that the gate stacks are subjected to in forming the capping layer induced dipoles that in turn influences the dipole related threshold voltage shifts and lowered gate leakage. By varying the position of the capping layers in the HfO2 gate dielectric, the threshold voltage and gate leakage are reduced by ~ 200mV and 1.5-2 orders of magnitude respectively in gate-last integration and ~580mV and 4 orders of magnitude respectively in gate-first integration.

This paper will focus on the capability of a low-temperature cyclical deposition/etch (CDE) epitaxy process based on Si2H6 to fabricate SiCP films exhibiting very-high, electrically-active P and C concentrations with fast growth rates. This process will be characterized on blanket wafers first and optimized for raised source/drain applications in planar FDSOI technology featuring 20nm design rules. Low temperature drive-in anneal in combination with high phosphorus doping was employed leading to best resistivity values of 0.3 mΩ.cm for SiP and 0.6 mΩ.cm for SiC2%P. We will show that increasing the phosphorus concentration in the layers enables us to have the same transistor overlap after diffusion anneal for comparable resistivity with SiP films and improved carbon substitutionality. Best Ron values as low as 220Ω.μm will be reported, measured on 20nm gate length transistors in planar FDSOI technology with an optimized process.

Future generations of silicon based integrated circuit technology require carrier concentrations in excess of the equilibrium dopant concentrations. In-situ doping during the epitaxial growth is an attractive alternative to place dopants where needed with tunable concentrations and hyper-abruptness. In this work we study the incorporation of boron or boron and carbon co-doping into fully strained high percentage (60%) Silicon-Germanium. We will discuss the epitaxial growth and dopant incorporation, and its effects on strain compensation due to the dopant atoms. The main focus will be on defect generation in highly strained doped SiGe layers.

FinFET is a promising device candidate for 14nm node CMOS technology. We have developed FinFET device showing superior short channel control at 25nm gate length. This FinFET device featuring gate first high-k/metal gate and merged Epi source/drain process. Key process improvements to resolve the FinFET unique challenges are presented. High drive currents have been obtained for both nFET and pFET. All these results show FinFET is the most promising candidate for 14nm node CMOS technology.

We have previously shown that by varying the position of threshold voltage adjustment cap layers within the gate stack, as well as the oxidant used during processing, it is possible to tune the threshold voltage of n-FET devices, and to concurrently realize a scaling benefit by incorporating group IIA and group IIIB elements into gate dielectrics deposited by metalorganic atomic layer deposition. In this report we have focused on lanthanum oxide cap layers that provide band edge nFET work functions. We compare our previously reported results with ozone oxidation with newly developed processes using oxygen and water as oxidants that result in highly scaled devices with band edge work functions and acceptable leakage characteristics.

This paper presents the optimization of HfO2 high-κ gate dielectrics by utilizing cyclic depositions and anneals during atomic layer deposition (ALD). An order of magnitude reduction in gate leakage is obtained by tuning the anneal temperature, duration and sequence in the ALD. The films are also seen to have three to four times reduction in carbon content. These optimized films are moreover observed to be densified without compromising equivalent oxide thickness (EOT), carrier mobility and threshold voltage. Further electrical characterization supports that there is a suppression of trap assisted tunneling with the optimized ALD process by revealing a stronger temperature dependence on the annealed samples as opposed to the conventional ALD process.

This paper presents studies performed in engineering high-k metal gate stacks by using capping layers containing Group IIA and IIIB elements. Both high-k gate dielectric (HfO2) and capping materials, namely, the oxides of barium, lanthanum and yttrium are deposited by atomic layer deposition (ALD) to offer superior process control and flexibility. Position specific insertion of cap layers into the gate stack is studied and the device tradeoffs are highlighted. The magnitude of Vt shift is correlated to the electronegativity of the cap layer species and its relative position in the gate stack. For a given cap position, BaO provides the maximum Vt shift, followed by La2O3 and Y2O3 caps. Ozone based ALD processes are shown to adversely impact Tinv scaling due to the re-growth of the interface layer between the high-k and the silicon substrate. Significant improvements in Tinv scaling are obtained by migrating to a water based ALD process.

In this work, co-sputtered TaC (tantalum + carbon targets + argon) and reactive sputtered TaC (tantalum + methane + argon) were evaluated and compared for application as metal electrodes in high-K/metal gate stacks aimed at 22 nm and beyond technology nodes. The electrical properties of field effect transistors (FETs) were evaluated as a function of TaC deposition conditions and optimized to achieve Tinv scaling. Controlling the deposition conditions as well as the composition of the TaC films was found to be critical to achieve Tinv < 11 Aå.

In this paper we will review some of our previous work on ALD deposited high-K dielectric stacks as well as present some of our more recent advances. We have shown that ALD can be used successfully to deposit high quality high-K gate dielectrics of Hf and Zr oxide. In addition, because of the inherent conformality of ALD processes, these dielectrics can be easily migrated to advanced device structures such as FINFETs. We have also been successful in developing ALD processes to deposit rare earth oxides (REOs), such as Y2O3 and La2O3. These processes are useful in creating layered dielectric structures where the REO functions as a threshold voltage adjustment layer. We use physical and electrical characterization of the films as deposited by ALD, including spectroscopic ellipsometry, corona oxide semiconductor charge measurement, TXRF, AES, angle resolved XPS, HRTEM, AFM, MEIS, and RBS, to provide information on the film growth mechanism and the primary parameters that influence the ALD growth of high-K oxides. We further correlate these findings with basic electrical results obtained from MOSFET and MOSCAP devices fabricated using our ALD processes to understand how process changes affect both the as-deposited films as well as the resulting devices.

The criterion for a suitable high-K dielectric/metal gate stack for replacing SiON/Poly-Si stacks in conventional CMOS devices are i) Equivalent oxide thickness (EOT) of {less than or equal to} 1.1 nm, ii) Electron and hole mobilities that are comparable to conventional stacks, and iii) Near Band-Edge (BE) threshold voltages for both nFET and pFET devices. Aggressive scaling and competitive mobilities have been demonstrated using HfO2/metal gate stacks [1] through optimization of interfacial layer composition, choice of suitable metal electrodes and deposition processes, and high thermal budgets that are compatible with conventional FET fabrication. A suitable NFET BE solution compatible with gate first process flow achieved by inserting capping layers containing gp. IIA (e.g., Mg) & gp. IIIB (e.g., La) elements into proven high mobility mid-gap HfO2/TiN gate stacks thereby moving the effective work function (EWF) to nFET BE [2,3]. On the pFET front, the challenge remains that elements with high bulk workfunction exhibit Vt instability as well as inherent scaling limitations after high temperature processing that is required in a gate first process flow.

The requirements for a high-k metal gate n-mosfet solution are that one has a device that exhibits a low Tinv (<1.5 nm), high mobility (~200 @ 1MV/cm) and a threshold voltage in the range of 0-0.2V. While these properties have been independently demonstrated, the key challenge has been to deliver these properties simultaneously and in a gate first , high temperature process flow. We show, that by introducing a new, ultrathin lanthanum oxide dielectric layer in the gate stack, whose function is to provide an electrostatic shift to the onset of threshold these requirements can be acceptably met. This is carried out without compromising gate capacitance and with minimal degradation to the mobility. The underlying physics behind the threshold shift will also be discussed.