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The gate-all-around thin-film transistor (TFT) (GAT) with thin channel poly-Si can suppress the individual performance variation induced by a poly-Si grain boundary in the channel, in addition to improving the average performance compared to the conventional single-gate TFT (SGT). This effect is attributed to the thinning of the effective channel poly-Si by half in the GAT. Poly-Si TFT simulation results clearly confirmed this effect in terms of the current(I)-voltage(V) characteristics and channel potential. The GAT also reduces the threshold voltage instability under negative bias temperature (-BT) stress because the GAT structure relaxes the stress electric field in the gate oxide. The high-performance GAT enables reduction of the size of the static random access memory (SRAM) cell by providing a large ON-current to the storage node and enhancing the data retention stability despite the low cell ratio. The GAT-SRAM cell is a strong candidate for SRAM of 16 Mb and beyond.

We propose a novel thin-film-transistor (TFT) structure named gate-all-around TFT (GAT). Its fabrication process is very simple, in that we realize the gate-all-around structure using only a dummy nitride pattern. The GAT shows high channel conductance and features of shield structure peculiar to the double-gate structure. It can also eliminate an anomalous leakage current which appears in the sub-half-micron regime. Combining this process with sacrifice oxidation of the channel poly-Si, we obtained a GAT whose performance is nearly equal to that of single-crystalline metal-oxide-semiconductor field-effect transistors (MOSFETs). Since the GAT requires only one additional mask layer and no increase in TFT area as compared with the conventional single-gate TFT, it is suitable for a high-density and low-cost static-random-access-memory (SRAM). SRAM cells with this GAT have the potential to exhibit performance equivalent to that of the full-complimentary-MOS (CMOS) cell.