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Reconfigurable FETs (RFETs) are ambipolar transistors featuring the ability to conduct both electrons and holes, which is often achieved through the use of silicon nanowires or similar gate-all-around topologies. In this article, we present initial results for standard cell synthesis based on our planar RFET device, featuring top-down planar silicon based technology, lower fabrication complexity than nanowire approaches and a high operating temperature robustness. We first introduce the device physics by explaining the structure and the operating principle on device level. We also summarize recent device optimizations to increase drive current and achieve symmetry between N- and P-type conduction. Next to CMOS-style standard cells, we present a reduced transistor count XOR cell and analyze timing. Transient simulations are performed entirely in TCAD to accurately show device performance. Further we describe extraction of relevant parameters of these circuits for usage in synthesis tools and compare our standard cells to a similar 180nmSOI technology. Afterwards we perform timing analysis for a full adder and explore the boundaries of our device with a larger cryptographic accelerator core. [ABSTRACT FROM AUTHOR]

In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device.

In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The fabricated MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure.

In this paper, we report on the fabrication and characterization of voltage-programmable (VP) nanowire (NW) field-effect-transistor (FET) devices suitable to enhance the flexibility in circuit design, such as of reconfigurable logic. Silicon NW-structures with mid-gap Schottky S/D junctions on silicon-on-insulator (SOI) substrate were fabricated performing as unipolar CMOS-like transistors. The desired device type, i.e. NMOS or PMOS, is programmed by application of a certain back-gate voltage. The programming capabilities of the devices fabricated using this approach are demonstrated experimentally using a VP-NW-CMOS inverter circuit on a multi-SOI-substrate like set-up.

In this work we investigate the in situgrowth of carbon nanotubes (CNTs) on different dielectric stacks for use in discrete field-effect transistor devices. While CNT growth is demonstrated on all stacks, only devices fabricated on atomic layer deposited aluminum oxide show sufficiently reliable gate dielectrics. Electrical burn pulses are applied to the devices to selectively remove undesired metallic CNTs in order to obtain proper transistor behavior with an on/off current ratio of five orders of magnitude.

High-temperature capable transistors are of great interest for industrial applications, for instance, oil & gas and geothermal exploration, avionic, space, automotive and energy conversion. Especially, energy conversion electronics using wide-bandgap power transistors, i.e. SiC- or GaN-based FET, in combination with high-temperature silicon gate-driver circuits can significantly increase system efficiency and reduce costs. Our improved planar virtually dopant-free silicon-based double gate SOI FET with reactively sputtered WTiNxfront-gate electrodes demonstrates ultra-low drain leakage currents at high-temperatures opening a path to record operating temperatures for silicon-based FET devices.

In this paper, we investigate by simulation and by evaluation of experimental data the feasibility of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect-transistor (FET) structure which is based on our already published Si-nanowire (SiNW) technology. The key technology for this dual-gated general purpose FET contains Schottky S/D junctions on a silicon-on-insulator (SOI) platform. In combination with electrostatic doping and a dual-gate configuration, the Schottky junctions significantly increase the temperature robustness of the device.