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An automatic inductor design process is helpful to reduce the design cycle of radio frequency (RF) integrated circuit (IC). This paper proposed an efficient synthesis-analysis machine (SAM) for on-chip inductor synthesis and modeling, as well as an automatic dataset generation (ADG) topology for the generation of artificial neural networks (ANNs) training dataset. The SAM consists of a synthesis ANN, two analysis ANNs and a proposed self-inspection machine (SIM). For a given design request, the SAM synthesizes a layout first, followed by analyzing the performance of the layout automatically, and finally improves the layout confidence through self-inspection. Compared to the modeling functions of analysis ANN, the synthesis ANN behaves as an inverse model, of which the inputs are desired inductor performances while the outputs are geometrical parameters of the layout. However, multi-value problems might occur in obtaining geometries of inductors, suggesting with evidence from mathematic relationships between geometrical and electrical parameters of an inductor. A multi-valued training dataset will mislead the synthesis ANN, resulting in unqualified layouts. To deal with this issue, a solution space contraction technique (SSCM) is also proposed. Furthermore, the SIM suspends most of the failures by comparing the output of analysis ANN back to the input of synthesis ANN. An electromagnetic simulation tool is used for experiments, and the effectiveness of the proposed SAM is proven by 6,500 inductor samples. [ABSTRACT FROM AUTHOR]

High step-up converters are often used in photovoltaic applications due to low voltage of photovoltaic modules. In this paper, a study of several voltage step-up cells added on primary and secondary sides of an isolated dc-dc SEPIC (single ended primary inductor converter) is made, in order to increase its static gain and synthesize a family of converters. To perform this study and select the most appropriate resulting converter, theoretical and comparative analyzes are accomplished. They include a brief description of each converter, tables and curves with relevant information, such as voltage gain, voltage stresses and component count, and the identification of the use of coupled inductor or transformer based on the analysis of dc magnetizing current. Moreover, theoretical analysis and experimental results on a 50 kHz and 200 W prototype of selected isolated SEPIC with voltage doubler cell are presented to validate the proposed topology and concept. [ABSTRACT FROM AUTHOR]

The series-capacitor boost converter (SCBC) requires a duty cycle ($D) \ge0.5$ control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that require CR < 4. Meanwhile, the $D \ge0.5$ control does not allow $D$ to increase smoothly from 0 during start-up, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows $D < 0.5$ without overstress or imbalance issues, thus extending the CR range and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3< CR < 4. We study the output impedance and CR expressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes’ ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of ${D}$ /(1 $+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz. [ABSTRACT FROM AUTHOR]

A new active building block namely, subtractor connected first-generation current conveyor (S-CCI) is introduced in this paper. A simulated floating inductor (SFI) and two new quadrature oscillators (QOs) employing only one S-CCI are introduced as application examples. The introduced SFI employs two resistors with a single matching requirement and a grounded capacitor. Each of the introduced QOs has one grounded resistor, one floating resistor, and two grounded capacitors without any matching problems. Non-ideality analyses are performed. Furthermore, a third-order filter application is given. A layout of the S-CCI in $0.18 \mu \text{m}$ technology occupying the area of about $71\,\,\mu \text{m}\,\,\times 44\,\,\mu \text{m}$ is given. Also, numerous post layout simulations based on the SPICE program are accomplished. Moreover, several experiments are realized to confirm the theory. [ABSTRACT FROM AUTHOR]

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50- $\Omega $ load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs. [ABSTRACT FROM AUTHOR]

In this paper, a Doherty power amplifier (DPA) using a novel three-port harmonic injection network (HIN) to extend its high-efficiency range is proposed. With the help of a part of the three-port HIN, which is placed between the carrier and peaking branches, the optimal drain fundamental frequency termination for the carrier device at back-off and saturation can be realized simultaneously thus enhancing the efficiency at back-off significantly. Meanwhile, this three-port HIN can also realize second harmonic drain terminations for the carrier and peaking device with the quasi-open and quasi-short circuit at the current plane, respectively. Consequently, the saturated power ratio between peaking and carrier devices is increased, which further extends the back-off range of the asymmetric drain-biased DPA. For demonstration purposes, an extended high efficiency range DPA was designed and fabricated using commercially available GaN HEMT (Cree CGH 40010F) devices. Measured results for this novel idea gave drain efficiencies better than 62.5% at 9-9.5 dB back-off point from 1.60 to 1.95 GHz. [ABSTRACT FROM AUTHOR]

This work presents a 25 MHz adaptive on/off-time-controlled three-level buck converter with a fast reference tracking speed and high light load efficiency. The self-balancing scheme of the flying capacitor voltage is revised and extended for a broad conversion ratio range from 0.17 to 0.833. To reduce the error of the self-balancing scheme when applied to a high frequency three-level buck converter with an on-chip flying capacitor, a real-time calibration loop on the flying capacitor voltage is introduced, effectively reducing the balancing error from 340 mV to 20 mV. A turning-point output voltage prediction for the three-level buck converter is presented to achieve near-optimal reference tracking with a fast tracking speed and negligible output voltage undershoot or overshoot. The up- and down-tracking takes 81 ns and 72 ns, respectively, for a 1-V step with an inductor of 47 nH and an output capacitor of 47 nF. The three-level converter achieves a precise discontinuous conduction mode (DCM) operation with an adaptive switching frequency at light load by means of a feedback loop-based method. An approximately 28.2% increment in efficiency is achieved with a load of 10 mA. The three-level buck converter has a peak efficiency of 92.8% and an over 85% efficiency in most of the operation regions. [ABSTRACT FROM AUTHOR]

In this paper, aiming to systematically derive single-inductor multi-input multi-output (SI-MIMO) converters having favorable merits of high-density and low-cost, a basic model is firstly extracted from the working principle. Theoretically, by enumerating all possible connections of the basic model and one-by-one manually judging their effectiveness according to working criterions, multiple viable SI-MIMO topologies can be obtained, but with heavy workload. To simplify the topology derivation process, this paper also proposes a computer-aided method to replace the manual effort. By modelling the basic model and working criterions with graph theory, MATLAB codes can be developed to automatically screen out the effective topologies. With the proposed method, 8 three-port, 28 four-port and 115 five-port converters with single inductor are conveniently obtained, including both the existing and new topologies. Moreover, by configuring ports and switches in each derived topology, multiple specific converters can be further expanded. These converters can provide more options for practical engineering applications, and a new topology is also introduced and experimentally verified in the paper. [ABSTRACT FROM AUTHOR]

In this paper, a highly efficient gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) Doherty power amplifier (DPA) from 4.6 to 5.5 GHz with the consideration of the influence of the peaking transistor’s output capacitor $(C_{\mathrm {out}}$) operated in Class-C state is presented. Based on the load-modulation behavior analysis, the effect of the $C_{\mathrm {out}}$ of the peaking transistor on the performance of the wideband DPA has been theoretically analyzed for the first time by directly evaluating the value of the peaking transistor’s $C_{\mathrm {out}}$. A hybrid matching technique has been proposed to ensure that the DPA can realize a proper load-modulation with high back-off efficiency in a wide bandwidth. In this method, the peaking transistor is matched using a simple T-shape band-pass type network with the $C_{\mathrm {out}}$ of the peaking transistor in Class-C operation state compensated properly, while the carrier transistor is matched using a 2-point matching method. For verification, a wideband GaN MMIC DPA with the frequency range of 4.6 to 5.5 GHz was designed using a 0.25- $\mu {\mathrm{ m}}$ GaN on silicon-carbon high-electron-mobility transistor process. Experimental results show that the fabricated DPA can realize the output power of 41.1-41.6 dBm and the drain efficiency (DE) of 57.6%-63.3% at saturation in the whole frequency band. The measured DE at 6-dB power back-off is 51%-56.4%. Good linearity with high average efficiency performance was obtained when excited by a 160-MHz modulated signal after linearization. [ABSTRACT FROM AUTHOR]

In a capacitive wireless power transfer system, due to the pF-level coupling capacitance, resonant inductors are commonly used at the primary side to boost voltage and at secondary side to boost the current. However, the inductors are bulky, in particular when it comes to integration, thereby not preferred by some space-sensitive applications like smartphones, smart glasses and headphones. This paper proposes a capacitive wireless power transfer architecture with no inductors at the receiver side. A high conversion ratio step down switched capacitor converter (SCC-CPT), rather than inductors, is used to compensate for the impedance mismatch between the secondary side of the capacitive coupler and the load. The analysis method and its associated design procedure of the SCC-CPT system is developed with the target of clarifying the tradeoffs among the secondary side efficiency, coupler voltage stress, receiver side integrability, and the primary side compensation network gain. Finally, a 7.5 W, 12 MHz SCC-CPT prototype was constructed to validate the proposed analysis and design. The measured system efficiency is 75.6 % at 7.5 W output, and the secondary side switched capacitor converter efficiency is 96.4 %. [ABSTRACT FROM AUTHOR]

This paper presents a multi-mode boost converter to achieve the high efficiency over a wide input voltage range for thermoelectric energy harvesting (TEH) applications. Under high, medium, and low input voltages, continuous conduction mode (CCM), critical conduction mode (CRM), and discontinuous conduction mode (DCM) are adopted to improve the conversion efficiency, respectively. Moreover, a constant peak current (CPC) control scheme is proposed to realize high efficiency under ultra-low input voltage. The proposed converter is implemented in a $0.18 \mu \text{m}$ standard CMOS process, which occupies a chip core area of about 1.0 mm $\times0.9$ mm. It achieves >60% efficiency in the range of TEG open-circuit voltage $V_{S}$ from 20 mV to 500 mV, and a peak efficiency of 91.4%. Moreover, after the startup is completed, an efficiency of 37.1% under the $V_{S}$ as low as 10 mV can be achieved. [ABSTRACT FROM AUTHOR]

With the rapid development of wireless technologies, the electromagnetic energy scattered in the environment becomes one of the most attractive energy sources for low power devices which are highly demanded in various applications. Since the available electromagnetic signals may have different frequencies, the corresponding receiving antenna and rectifier are required to support multi-band operation to obtain as much energy as possible. However, existing multi-band rectifiers usually have a complex structure or unsatisfactory performance. For this issue, a self-matched rectifying structure is proposed. The theoretical analysis of the proposed configuration demonstrates the unique self-matched characteristics, which is important to implement multi-band operation with simplicity in design procedure and structure. For validation, two rectifiers are designed, fabricated and measured. The dual-band rectifier achieves measured conversion efficiencies of 69.37% and 55.28% at 2.38 GHz and 4.99 GHz with 5 dBm input power in actual measurement, respectively. Owing to the self-matched property, a tri-band design operating at 1.78 GHz, 2.35 GHz, and 4.97 GHz can be easily implemented and achieve efficiency of 60.95%, 71.37%, and 54.01% under test, respectively. Compared with the existing works, the proposed rectifier has high simplicity in both design and structure maintaining high conversion efficiencies at different frequencies. [ABSTRACT FROM AUTHOR]

In this paper, a high-order nonlinear disturbance observer-based fractional-order sliding mode control (FOSMC) strategy is proposed for DC/DC buck converters in the presence of mismatched disturbances, ensuring the properties of both stability and dynamic performance. Traditional sliding mode control can deal with matched disturbances while achieving desired closed-loop performance, unfortunately it is particularly sensitive to mismatched disturbances. In the proposed control structure, two nonlinear disturbance observers are constructed to estimate both matched and mismatched disturbances in finite time. Then, the estimated variables are used for the fractional-order sliding mode surface design, where a super twisting sliding mode controller is designed to drive the states of the system to track their desired values. Comparing with the traditional SMC, the proposed method not only reduces the sensitivity of the system to mismatched disturbance, but also improves the transient performance of the system. Simulation and experimental results have comprehensively illustrated the feasibility and effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

In this paper, the design of a 77.3 GHz Standing-Wave oscillator (SWO) is presented. The proposed SWO relies on the distribution of varactors along an asymmetrical slow-wave coplanar stripline, which enables the improvement of the quality factor of the tunable resonator, resulting in superior performance in terms of phase noise and DC-to-RF efficiency. The design methodology, based on the use of analytical models and abaci, is presented in detail and applied to a design in a 55-nm CMOS technology. With a core consumption of 15.1 mW, the proposed SWO operates from 76.09 GHz to 78.60 GHz and presents a phase noise of −115.1 dBc/Hz at 10 MHz offset, leading to a Figure of Merit (FOM) of −181 dBc/Hz. The DC-to-RF efficiency obtained is 3.1%. [ABSTRACT FROM AUTHOR]

Sufficient conditions are established for the exponential stability/instability of the equilibrium profiles for a linearized model of nonisothermal axial dispersion tubular reactors. The considered reactors are assumed to involve a chemical reaction of the form $ A \to B$ , where $ A$ and $ B$ denote the reactant and the product, respectively, and where the Peclet numbers appearing in the energy and mass balance partial differential equations are assumed to be equal. First, different kinds of linearization of infinite-dimensional dynamical systems are presented. Then, the considered linearized model around any equilibrium is shown to be well-posed. Moreover, by using a Lyapunov-based approach, exponential stability is addressed. In the case when the reactor can exhibit only one equilibrium, it is shown that the latter is always exponentially stable. When three equilibrium profiles are exhibited, bistability is established, i.e. the stability pattern “(exponentially) stable—unstable—stable” is proven for the linearized model. The results are illustrated by some numerical simulations. [ABSTRACT FROM AUTHOR]

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A. [ABSTRACT FROM AUTHOR]

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL’s phase detector (2.7–4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of −232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of −247dB, and normalized TR and area (FOMTA) of −262dB. [ABSTRACT FROM AUTHOR]

This article presents a comprehensive analysis of a novel broadband output stage for external RF front-end low-noise amplifiers (eLNAs). Both variants of the output stage are manufactured using a 130nm bulk CMOS technology. They utilize a common-drain output stage with current-reuse topology, switchable resistive feedback, and source-degeneration. Also, a novel inductor-less low insertion-loss bypass mode is implemented for enhanced bypass functionality. The LNAs are implemented with 4 gain modes achieving excellent RF performance in all possible mobile communication scenarios. Furthermore, an auxiliary linearization circuitry (NMOS IMD sinker) is implemented for variant β to improve linearity performance in low gain mode. Besides, the LNAs support all frequency bands between 1.4GHz and 2.7GHz by only changing the external matching component, allowing easy adaption to different frequency bands. Two offered solutions are realized with a die size of only 0.16mm2 and 0.11mm2, respectively. The power consumption is 6.0mW in high gain, 3.6mW in low gain and active-bypass and 0.12mW in bypass mode using a supply voltage of 1.2V. Moreover, a 5.15GHz LNA with high-Q on-chip matching and the broadband output stage is realized and manufactured using a 60nm RF SOI technology. A NF performance of only 1.15dB is achieved consuming only 6.0mW power. [ABSTRACT FROM AUTHOR]

This paper proposes a novel artificial neural network (ANN) based control method for a dc/dc buck converter. The ANN is trained to implement optimal control based on approximate dynamic programming (ADP). Special characteristics of the proposed ANN control include: 1) The inputs to the ANN contain error signals and integrals of the error signals, enabling the ANN to have PI control ability; 2) The ANN receives voltage feedback signals from the dc/dc converter, making the combined system equivalent to a recurrent neural network; 3) The ANN is trained to minimize a cost function over a long time horizon, making the ANN have a stronger predictive control ability than a conventional predictive controller; 4) The ANN is trained offline, preventing the instability of the network caused by weight adjustments of an on-line training algorithm. The ANN performance is evaluated through simulation and hardware experiments and compared with conventional control methods, which shows that the ANN controller has a strong ability to track rapidly changing reference commands, maintain stable output voltage for a variable load, and manage maximum duty-ratio and current constraints properly. [ABSTRACT FROM AUTHOR]

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2 active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design. [ABSTRACT FROM AUTHOR]

We develop an approximate frequency-independent equivalent circuit for integrated inductors on semiconducting substrates. All values of LCR in the equivalent circuit can be calculated directly from inductor geometry. The equivalent circuit captures: the skin effect, the proximity effect, the substrate capacitive loss, and the distributed capacitance. With careful definition of inductor quality factor, we are able to calculate the contribution of substrate capacitive loss and benefits of a substrate shield. Our model was put to test by successfully predicting the published quality factors of various inductors and proving that their geometries are close to optimum. [ABSTRACT FROM AUTHOR]

This paper presents a time-division-multiplexed (TDM) clocked-analog low-dropout regulator (CLDO) that shares one controller between multiple output channels. Clocked-analog operation is introduced to create idle periods that enable the shared controller to independently regulate different output channels through time-division multiplexing. Furthermore, an asynchronous transient enhancing technique is presented. Thanks to the controller sharing, the TDM CLDO is more area-efficient than conventional designs for supplying multiple outputs, especially when power stages and on-chip loads are small. To verify the effectiveness of the TDM CLDO, a dual-channel version is fabricated in a 130 nm CMOS process. Measurement results show that it can independently track two 100 kHz $0.3~\rm V_{pp}$ sinusoidal signals with 4 mV average output error at $100~\Omega $ load and 6 MHz clock frequency. For load transient responses, it can independently regulate two output channels to 1.05 V and 0.95 V with 41 mV/88 mV and 67 mV/39 mV overshoot/undershoot when both channels experience 5 mA current steps at $1.2~\rm V_{dd}$. To the best of our knowledge, this is the first time that hardware sharing is implemented for continuous closed-loop systems. [ABSTRACT FROM AUTHOR]

This paper presents the design and measurement of an RF energy harvesting and power management unit that operates across a wide range of available input power, from −24 to +15dBm. The system comprises an adaptive impedance matching network, a single-stage cross-coupled differential-drive rectifier, a start-up charge pump, an adaptive buck-boost converter, a maximum power point tracking (MPPT) circuit and a control loop to regulate the load voltage. The MPPT circuit controls the switching frequency of the buck-boost converter and configures the impedance matching network, optimizing the interfaces between the rectifier and antenna and between the rectifier and the storage capacitor, guaranteeing that the power is being harvested at maximum efficiency. To boost the rectifier output, to accumulate energy in the storage capacitor and to provide energy to the load, a single-inductor buck-boost converter that has two inputs and three outputs is used. Circuit techniques that reduce the power consumption of the control circuits and that allow for adapting the interfaces between the antenna, the rectifier and the load are presented. The peak harvesting efficiency of the system is 40.2%, when presented with an RF source of -9.1dBm available power and 403.5MHz frequency. [ABSTRACT FROM AUTHOR]

This article deals with a class of resistive–inductive–capacitive (RLC) circuits and switched RLC (s–RLC) circuits modeled in the Brayton–Moser framework. For this class of systems, new passivity properties using a Krasovskii-type Lyapunov function as storage function are presented, where the supply rate is function of the system states, inputs, and their first time derivatives. Moreover, after showing the integrability property of the port-variables, two simple control methodologies called output shaping and input shaping are proposed for regulating the voltage in RLC and s–RLC circuits. Global asymptotic stability is theoretically proved for both the proposed control methodologies. Moreover, robustness with respect to load uncertainty is ensured by the input shaping methodology. The applicability of the proposed methodologies is illustrated by designing voltage controllers for dc–dc converters and dc networks. [ABSTRACT FROM AUTHOR]

This paper presents a systematic approach to synthetize constant power loads using switching converters under sliding-mode control. The generation of sliding motions is analyzed in converters with a series inductor in the input port and a switching function representing the error between the input power and a suitable power reference. The analysis establishes the existence conditions for sliding-mode and the stability of the resulting ideal dynamics. Simulation and experimental results verifying the theoretical predictions in boost, Ćuk and SEPIC converters illustrate the proposal. The design procedure yields a simple, economical and small-size prototype that can be useful in the experimental validation of converters supplying constant power loads. [ABSTRACT FROM AUTHOR]

In this article, first integrated circuit (IC) implementation of parallel synchronized switching harvesting on inductor (p-SSHI) is presented for triboelectric energy harvester targeting 1 Hz to 5 Hz mechanical motions. It is accompanied by on-chip buck and switched capacitor DC-DC converters, all capable of handling 70 V levels. Unlike piezoelectric harvesters, triboelectric nanogenerators (TENGs) can produce very high open-circuit voltages; thus, the proposed system utilizes this property within the technology limits to maximize the extracted power. An in-house manufactured TENG using steel and polytetrafluoroethylene (PTFE) is modeled for sub-5 Hz motions. The energy is extracted and stored in an external capacitance until its voltage reaches 70 V, which is achieved in three press-and-release mechanical cycles. 70-to-2 V down conversion is carried on by 70-to-10 V buck converter followed by a 10-to-2 V switched capacitor DC-DC converter. A chip is manufactured in $0.18~\mu \text{m}$ HV BCD process with an active area of 6.25 mm2. End-to-end peak efficiency is measured as 32.71% for 1 Hz motion with a 722 $\mu \text{W}$ total power delivery to the load for 4 ms. [ABSTRACT FROM AUTHOR]

The paper considers a relevant class of networks containing memristors and (possibly) nonlinear capacitors and inductors. The goal is to unfold the nonlinear dynamics of these networks by highlighting some main features that are potentially useful for real-time signal processing and in-memory computing. In particular, an analytic treatment is provided for dynamic phenomena as the presence of invariant manifolds, the coexistence of different regimes, complex dynamics and attractors and the phenomenon of bifurcations without parameters, i.e., bifurcations due to changing the initial conditions of the state variables for a fixed set of circuit parameters. The paper also addresses the issue of how to design pulse independent voltage or current sources to steer the network dynamics through different manifolds and attractors. Two relevant examples are worked out in details, namely, a variant of Chua’s circuit with a memristor and a nonlinear capacitor and a relaxation oscillator with a memristor and a nonlinear inductor. In the latter example, the paper also studies the effect on manifolds and coexisting dynamics when real memristive devices are accounted for using a class of extended memristor models. The analysis is conducted by means of a recently developed technique named flux-charge analysis method (FCAM). Numerical simulations are presented to confirm the theoretic findings. [ABSTRACT FROM AUTHOR]

This paper presents a self-startup power management IC (PMIC) applicable in thermoelectric generators (TEGs). The PMIC is based on a boost converter integrated with a complete control circuitry that handles all required operations, including maximum power point tracking (MPPT). The converter supports cold self-start from low TEG voltages using three startup phases and two power-on-reset (POR) signals for smooth transitions between the phases. The PMIC is designed and fabricated in a 180-nm technology. The cold-start operation is verified at a minimum TEG voltage of 60 mV. The converter achieves a peak efficiency of 79.94% at 120-mV input voltage and $1080~\mu \text{W}$ output power, while maintaining efficiency above 70% for a wide range of TEG voltage from 80 mV. [ABSTRACT FROM AUTHOR]

This article presents a compact power management solution for a pipeline analog-to-digital converter (ADC), employing only a switching-mode power converter. By directly powering the ADC using a boost DC-DC converter, the power delivery network (PDN) exhibits an overall-high power efficiency. The proposed foreground ADC calibration calibrates the ripple error induced from the power converter, which obviates the need for well-regulated supply and reference voltage offered by low-efficiency linear low-dropout regulators (LDOs). A chip integrates the boost DC-DC converter and the pipelined ADC with an external power inductor. The prototype, implemented in 65-nm CMOS, occupies 2.34-mm2 of total active area (9.4% - ADC, 2.6% - power controller and switches, and 88% - output capacitance). In the measurement, the boost converter, switching at 31.25MHz, converts a 0.5V input to 1.2V and delivers 22.8mW of power to the pipeline ADC. The boost DC-DC converter supplies all voltage domains, including analog/digital power supply and reference. The resulting overall system power efficiency is 78.6%. Sampled at 500MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 34.7/39.9dB without/with the ripple calibration for an input frequency of 177MHz, respectively. [ABSTRACT FROM AUTHOR]

This article presents a 22–47 GHz wideband low-noise amplifier (LNA) with coupled L-type interstage matching inductors. The coupled inductors extend the bandwidth of LNA by moving zeros to lower frequencies to cancel the effect of poles. Meanwhile, asymmetric L-type inductors with different inductances can be designed separately to achieve better gain flatness. In addition, the quality factor of coupled inductors is also slightly improved without significantly changing their inductance. The LNA is fabricated in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, and it occupies a core area of 0.13 mm2. The LNA achieves a peak gain of 22.2 dB with the 3dB bandwidth of 22–47 GHz (fractional bandwidth up to 72.5%). The measured NF varies between 3.0 and 4.3 dB from 22 to 47 GHz. The measured input 1-dB gain compression point is stable from −23.9 to −22.6 dBm in the entire 3-dB gain bandwidth. The chip consumes a total power of 9.5 mW from a 1.2 V supply. [ABSTRACT FROM AUTHOR]

A simple simultaneous frequency- and power-dividing ratio- reconfigurable quadrature coupler using lumped elements is presented for reconfigurable radio applications. The theoretical analysis shows it can achieve perfect matching and isolation at all tuning states. The closed-form design equations are derived. For verification, a simultaneous frequency- and power-dividing ratio-reconfigurable quadrature coupler is designed based on the design equations. The measured 3-dB quadrature coupler is tuned from 1.8 GHz to 4.36 GHz with return loss and isolation of better than 20 dB. In addition, the measured power-dividing ratio can be tuned from −16 to 5.0 dB at 3 GHz while maintaining 20-dB return loss and isolation. As compared with state of the arts, the main merit of the proposed quadrature coupler is achievement of simultaneously wide tuning range of frequency and power-dividing ratio with the simple tuning mechanism and improved amplitude balance performance. [ABSTRACT FROM AUTHOR]

In this paper, four control strategies for DC-DC buck converters are proposed, compared and analyzed: a single-loop adaptive control strategy (SA), a double-loop adaptive control strategy (DA), a single-loop disturbance observer-based control strategy (SDOB) and a double-loop disturbance observer-based control strategy (DDOB). First, the nominal system without considering the parametric uncertainties of the DC-DC buck converter is built to help develop the SA and DA. The SA is built by adaptive and backstepping control approaches, and the DA is set up by adaptive and sliding mode control approaches. Additionally, a model considering parametric uncertainties is introduced, giving the opportunity to develop the SDOB and DDOB. The SDOB is developed using a designed disturbance observer and backstepping control technique, and the DDOB is synthesized using a designed disturbance observer and sliding mode control method. Finally, the advantages and disadvantages of the four proposed control strategies are compared and analyzed through experiments. [ABSTRACT FROM AUTHOR]

This paper presents a wide-tuning range dual-mode millimeter wave (mm-wave) voltage controlled oscillator (VCO) incorporating high quality-factor (Q) transformer-based variable inductors. A high Q switched inductor with two different values is proposed by constructing the load of a transformer of a high Q fixed capacitor in series with a lossless switch structure that does not add any loss to the LC-tank as implemented by changing the signals mode across the capacitor. By choosing a proper center frequency for each mode and sufficient frequency overlap, a wide frequency tuning range (FTR) mm-wave VCO can be designed. It provides almost twice higher tuning range while keeping phase noise (PN) nearly the same as the two-mode VCO designed with two standalone inductors. Fabricated in a 65 nm CMOS process, the VCO demonstrates the measured FTR of 22.8% from 64.88 to 81.6 GHz range. The measured peak PN at 10 MHz offset is -114.63 dBc/Hz and the maximum and minimum corresponding figures of merit FOM and FOM $_{\mathbf {T}}$ are -173.9 to -181.84 dB and -181.07 to -189 dB, respectively. The VCO cores consume 10.2 mA current from 1 V power supply, and the occupied area is $0.146\times 0.205$ mm $^{\mathbf {2}}$. [ABSTRACT FROM AUTHOR]

This paper revisits the behavioral modeling of inductors used for Switch-Mode Power Supply (SMPS) design. A novel unified behavioral modeling for power inductors is herein proposed, which considers the DC current passing through the device and the equivalent applied voltage and switching frequency as model inputs, and the resulting peak-to-peak current ripple, total power loss and temperature as model outputs. The proposed behavioral modeling relies on simple analytical formulas, discovered from experimental measurements by using a multi-objective evolutionary algorithm. The resulting behavioral models allow to define the “Constrained Operating Area” of a power inductor, which describes the boundary area in the three-dimensional domain of switching frequency, DC current and equivalent voltage that can be applied to the component while maintaining its peak-to-peak current ripple, power loss and temperature within given limits. The experimental case studies presented in the paper eventually confirm the reliability of the proposed behavioral modeling approach and of the resulting models, in the assessment of the suitability of a given inductor and in the comparative evaluation among different inductors for a given SMPS application. [ABSTRACT FROM AUTHOR]

This paper presents various techniques to achieve high efficiency for the bidirectional Cascaded-Buck-Boost converter. This converter has the features of low voltage across the switches and positive output voltage. The objective of this paper is to optimize the magnetics design to reduce the total losses in a low power non-isolated DC-DC circuit. A rigorous loss model with component nonlinearities is developed to determine the power loss distribution. It is validated by simulations and experiments. Based on the results of the power loss analysis and due to the low inductor profile and high efficiency target, nanocrystalline material will be the best candidate. Therefore, a new small volume low profile planar-nanocrystalline inductor is designed. Various deep de sign aspects for core and copper are discussed. The Finite-Element-Analysis (FEA) method is used to examine and visualize the inductor design. By implementing the planar-nanocrystalline inductor, a California Energy Commission (CEC) weighted efficiency of 99.05% for the buck mode and 98.98% for the boost mode are achieved with a peak efficiency of 99.24% and 99.21%, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a piecewise quadratic slope compensation technique for eliminating subharmonic oscillations in dc-dc switching converters is studied. With this technique, a self-generated signal is used in the compensation scheme resulting in a naturally full duty cycle stability domain. The expression of the piecewise quadratic compensating signal within a switching cycle is derived. It is obtained that the steady-state value of the amplitude of this signal is the same as in the conventional linear slope compensation scheme that guarantees stability for all values of the duty cycle. However, in the piecewise quadratic scheme this is achieved without exact knowledge of the inductance value nor sensing the input and the output voltages. The stability of the converter under the considered compensation scheme is also guaranteed for all values of the duty cycle with voltage loop open. A boost converter under peak current mode control is used to validate the theoretical results both by numerical simulations and by experiments. Simulation results are analyzed and compared to the performances of the state-of-art techniques with voltage loop closed. [ABSTRACT FROM AUTHOR]

An important open problem in the synthesis of passive controllers is to obtain a passive network that realizes an arbitrary given impedance function and contains the least possible number of elements. This problem has its origins in electric circuit theory, and is directly applicable to the cost-effective design of mechanical systems containing the inerter. Despite a rich history, the problem can only be considered solved for networks that contain at most two energy storage elements, and in a small number of other special cases. In this article, we solve the minimal network realization problem for the class of impedances realized by series–parallel networks containing at most three energy storage elements. To accomplish this, we develop a novel continuity-based approach to eliminate redundant elements from a network. [ABSTRACT FROM AUTHOR]

A millimeter-wave current-reuse voltage-controlled oscillator (VCO) features a single-turn multi-tap inductor and two separate differential-only switched-capacitor arrays to improve the power efficiency and phase noise (PN). Specifically, a single-branch complementary VCO topology, in conjunction with a multi-resonant Resistor-Inductor-Capacitor-Mutual inductance (RLCM) tank, allows sharing the bias current and reshaping the impulse-sensitivity-function. The latter is based on an area- efficient RLCM tank to concurrently generate two high quality- factor differential-mode resonances at the fundamental and 2nd- harmonic oscillation frequencies. Fabricated in 65-nm CMOS technology, our VCO at 27.7 GHz shows a PN of −109.91-dBc/Hz at 1-MHz offset (after on-chip divider-by-2), while consuming just 3.3 mW at a 1.1-V supply. It corresponds to a Figure-of-Merit (FOM) of 187.6 dBc/Hz. The frequency tuning range is 15.3% (25.2 to 29.4 GHz) and the core area is 0.116 mm2. [ABSTRACT FROM AUTHOR]

For the first time, this work presents a wireless-wireline hybrid 3D interconnect that employs orthogonal simultaneous bidirectional signaling for 3D Network-on-chip to achieve $2\times $ bandwidth density. We combine wireless near-field inductive coupling channel (NFIC) encompassing wireline through-silicon vias (TSV) to leverage orthogonal simultaneous bidirectional (SBD) signaling. This technique provides an efficient way of doubling interconnect bandwidth in the same area by means of passive wireless and wireline interconnects. The proposed hybrid 3D interconnect shows at least -70dB of NFIC-TSV isolation in the band of interest. We also present a comprehensive link analysis to derive the energy-area trade-off of an NFIC link and its fundamental performance limits. Further, we demonstrate on how equalization has the potential to decouple the fundamental energy-area tradeoff. The prototype transceiver measures a simultaneous bidirectional data and clock communication at an effective data rate of 6.6 Gb/s consuming 263 fJ/bit in 65 nm CMOS bulk process. The developed hybrid 3D interconnect architecture exhibits a $2\times $ improved link performance over state-of-the-art 3D simultaneous bidirectional links. A hybrid 3D Network-on-chip (3D NoC) implementation is demonstrated using the proposed hybrid interconnect technology and shows a 50% lower area and cost for the same energy-delay-product (EDP) over the conventional TSV based links. [ABSTRACT FROM AUTHOR]

This article presents a high-conversion-ratio (HCR), high-voltage-tolerant (HVT) energy-harvesting battery charger using 0.18- $\mu \text{m}$ standard CMOS for Internet of Things (IoT). To reduce conversion ratio (CR) of inductive power converter and optimize overall power efficiency, the proposed charger cascades a boost converter and reconfigurable charge pump. Different from the high-voltage device, the standard CMOS process has lower parasitic capacitance and on-resistance; therefore, it can reduce switching and conduction loss. The reconfigurable charge pump dynamically changes the number of pumping stages according to the output voltage ($V_{{OUT}}$) by automatic configuration selector (ACS). To manage the limited power from a thermoelectric generator (TEG), the converter works under the discontinuous conduction mode (DCM). The zero-current detector (ZCD) employs an analog comparator with digital offset compensator and digital comparator to control off-time ($T_{{OFF}}$) quickly and accurately. The self-idle constant on-time (SI-COT) and idle mode both control the mechanism, helping to further reduce static power dissipation. As a result, the proposed converter can achieve peak efficiency of up to 76% at a $92\times $ conversion ratio with output power ranging from $10~\mu \text{W}$ to 1.9 mW. The available input voltage ranges are 40 to 400 mV, and the dual output voltage ranges are 1 to 1.6 V and 2 to 4.6 V for $V_{{BOOST}}$ and $V_{{OUT}}$ , respectively. [ABSTRACT FROM AUTHOR]

Present universal serial bus (USB) battery chargers often suffer from limitations to meet the increasing demand for quick charging due to compromised power efficiency and complicated hardware implementation. In this paper, we propose a charge unifiable (QU) control scheme that enables a battery charger to improve power efficiency in a low-profile hardware manner. This scheme features fully soft-switching (vis-à-vis hard switching) and single control scheme (vis-à-vis multiple) for distinct constant current (CC) and constant voltage (CV) charging modes. To the best of authors’ knowledge, the proposed QU control scheme is the first to simultaneously offer fully soft-switching, innate CC-and-CV regulation, and seamless CC-to-CV transition. To verify the proposed design, we monolithically realize a low-profile high-efficiency fast battery charger based on this scheme. The prototype embodying a tiny 470-nH output inductor supports a maximum input voltage of 16V, output voltage of 2.2-4.2 V, output current of 0.1-2 A, and peak power efficiency of 96.2%. When benchmarked against state-of-the-art counterparts, the proposed charger features at least $2.1\times $ smaller inductor and 7.2% higher power efficiency at both the maximum and the minimum output power charging scenarios. Further, this charger is the only design that features ≥91% power efficiency in the whole load range. [ABSTRACT FROM AUTHOR]

Optimal voltage-controlled oscillator (VCO) design for ultralow-power (ULP) radios has to fulfill simultaneously multiple requirements such as frequency tuning range, phase noise, power consumption, and frequency pushing. The manual design struggles to approach the full potential that a given topology can achieve. In this work, we prove the role of electronic design automation (EDA) tools by fully supporting the complex design of a ULP complementary Class-B/C hybrid-mode VCO. In the 1st step of the EDA-assisted flow, we perform a worst-case corner of worst-case tuning sizing optimization over a 108-dimensional performance space, offering sizing solutions with power consumption down to $145~\mu \text{W}$ at the worst-case. In the 2nd step, we introduce an automatic layout generation tool to offer valuable insights into the post-layout design space and devise a ready-for-tape-out fine optimization strategy. The hybrid-mode VCO prototyped in 65-nm CMOS occupies a die area of 0.165 mm2 and dissipates $297~\mu \text{W}$ from a 0.8 V supply at 5.1 GHz. The phase noise at 1 MHz offset is −110.1 dBc/Hz, resulting in a competitive Figure-of-Merit (FoM) of 189.4 dBc/Hz well-suited for ULP applications. [ABSTRACT FROM AUTHOR]

This paper presents an IC that extends the voltage capability of a low voltage battery charger to 100V for accurately and reliably charging lithium ion (Li-Ion) battery stacks of up to 18 cells. The IC interfaces with a buck converter battery charger that utilizes external nFET control and an external inductor current sensing resistor. The voltage extender IC provides voltage level translation for the nFET control signals and the current sensing function while supporting an input power supply voltage of up to 100V and output battery voltage of up to 80V. The inductor current sense voltage is translated with a ping-pong amplifier capable of driving a bi-directional input voltage to a fully differential output with a maximum load current of 10 mA at 20 MHz bandwidth and less than $500~\mu \text{V}$ offset. The combined system of the voltage extender IC and battery charger achieved 97% efficiency at a 4-A charging current. The battery charging voltage accuracy was better than ± 0.5% at 80V. [ABSTRACT FROM AUTHOR]

In this paper, we propose an observer for a dynamical system for which the states on the frontier of its domain are not observable, and all trajectories converge to the frontier. The proposed case study, a bioreactor in batch operating conditions with a single microbial reaction and gas production, is standard and largely encountered in practical situations. We also show how to extend this observer to obtain an observer in higher dimension that is robust with respect to unbiased noise. [ABSTRACT FROM AUTHOR]

In this paper, the start-up response of a digitally controlled dc-dc boost converter with a constant power load is studied. A mathematical expression of the system response during start-up is derived using a nonlinear averaged model. The time-domain response of the system during start-up when the converter is operating under current limitation mode is derived by analytically integrating the mathematical equations describing the dynamic behavior. Numerical simulations from a detailed switched model validate the theoretical results and a good agreement is obtained. A boost converter prototype is built to validate the theoretical finding and the numerical simulations. It is observed that even when the analysis and the simulation predict zero inrush current, the experimental circuit still exhibits an unsuitable initial current peak and an unacceptable transient response during start-up. This phenomenon is mainly attributed to the presence of an unavoidable delay due to the computation time required by the digital control platform. The resulting inrush current is more pronounced in the presence of nonlinear load such as a CPL and saturable inductor. Some solutions are proposed to mitigate the inrush current problems. Simulations results taking into account the delay and experimental measurements demonstrate the validity of the proposed solutions. [ABSTRACT FROM AUTHOR]

This paper deals with the analysis of the nonisothermal axial dispersion tubular reactor. The existence of equilibrium profiles is investigated. In particular, for equal Peclet numbers, it is shown that one or three equilibria can be exhibited, depending on the parameters of the system, especially on the diffusion coefficient. In addition, different and close Peclet numbers are also considered. In these cases, it is also shown that the reactor has one or three equilibrium profiles. Some numerical simulations support the theoretical results. [ABSTRACT FROM AUTHOR]

In this work, a new type of miniaturized on-chip resonator using coupled-inductor structure is presented. The impact on resonances of the structure due to the use of non- inverting- and inverting-coupled configuration is extensively investigated. It has been found that using the inverting-coupled structure, a stronger resonance can be generated, which is ideally suitable for device miniaturization. To fully understand the working mechanism of the resonator and use it effectively for bandpass filter (BPF) design, simplified LC equivalent-circuit models and detailed theoretical analysis are provided. To further demonstrate the proposed concept is useful in practice, not only a 1st-order BPF, but also another two 2nd-order BPFs are designed and fabricated in a standard 0.13- $\mu \text{m}$ (Bi)-CMOS technology. All of them are designed to have a centre frequency around 15 GHz. Their physical dimensions are $0.13\times0.25$ mm2, $0.26\times0.25$ mm2, $0.24\times0.22$ mm2, respectively. Good agreements between simulation and measurement have been obtained, which verify that the presented design approach is suitable for miniaturized on-chip passive design. [ABSTRACT FROM AUTHOR]

The objective of this paper is to demonstrate that the use of a distributed approach for the design of the inductance of an LC-tank millimeter-wave (mm-wave) voltage-controlled oscillator (VCO) can lead to higher performance. Performance is improved in both frequency tuning range and power consumption thanks to a reduction of the cross-coupled pair size. The direct comparison of VCOs designed in different technologies is not straightforward, since the performance of the varactors and the inductance widely differ for different fabrication technologies. Hence, two VCOs were designed and integrated in the same CMOS 55-nm technology by using the same varactors. A “classical” VCO using an inductor available in the technology and serving as reference, and a distributed-inductance-based VCO using a slow-wave transmission line were considered. A detailed and efficient approach is adopted for the synthesis of slow-wave transmission line-based inductance without using time-consuming EM simulations. The slow-wave VCO permits to limit the overall size linked to a distributed approach while improving the electrical performance. The experimental results on the proof-of-concept demonstrators at a working frequency of 77 GHz allow validating our proposal. [ABSTRACT FROM AUTHOR]

THE JOKE HAS BEEN AROUND almost as long as the dream: Nuclear fusion energy is 30 years away…and always will be. But now, more than 80 years after Australian physicist Mark Oliphant first observed deuterium atoms fusing and releasing dollops of energy, it may finally be time to update the punch line. [ABSTRACT FROM AUTHOR]