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Digital circuits based on nanoelectromechanical (NEM) relays hold out the potential of providing an energy efficiency unachievable by conventional CMOS technology. This paper presents a detailed analysis of the operating characteristics of fabricated curved cantilever NEM relays using a comprehensive physical model. The mode of energy distribution within the electrical and mechanical operational domains of the relay is described in detail and the energy saving achievable by the technique of body-biasing is quantified. The analysis further reveals that the latency in a relay can be much larger or much smaller than the nominal mechanical delay depending on the point of actuation in the oscillation of the beam that takes place after pull-out. The methods that can utilize this phenomenon to reduce the latency of relay-based circuits are discussed, thus addressing one of the biggest challenges in NEM relay-based design. [ABSTRACT FROM AUTHOR]

A fully integrated 256-Mcell multi-level cell (MLC) phase-change memory (PCM) chip in 90-nm CMOS technology is presented. The on-chip circuitry supports fast MLC operation at 4 bit/cell. A programmable digital controller is used to optimize closed-loop gain and timing of the iterative MLC programming scheme and two power-efficient 8-bit DACs support current-controlled as well as voltage-controlled write pulses. The read-out consists of a low-power auto-range frontend followed by a 6-bit cyclic ADC that converts the nonlinear PCM resistance in a range between 10 k\Omega and 10 M\Omega. A verilog-A model derived from a full 3-D simulation of the PCM cell was developed to simulate the complete chip. The chip was used to demonstrate operation at 2 bit/cell and programming below 10 \mus with Ge2Sb2Te5 (GST) based PCM cells at a raw bit error rate of \sim 2 \times 10^- 4. Two main roadblocks for MLC PCM are drift and endurance. The accuracy of the analog frontend in combination with the programmable controller enables drift mitigation at the system level and the exploration of new materials for MLC operation at 3+ bit/cell. [ABSTRACT FROM PUBLISHER]

This paper presents a monolithic chemical gas sensor system fabricated in industrial CMOS-technology combined with post-CMOS micromachining. The system comprises metal-oxide-covered (SnO2) micro-hotplates and the necessary driving and signal-conditioning circuitry. The SnO2sensitive layer is operated at temperatures between 200 and 350°C. The on-chip temperature controller regulates the temperature of the membrane up to 350°C with a resolution of 0.5°C. A special heater-design was developed in order to achieve membrane temperatures up to 350°C with 5 V supply voltage. The heater design also ensures a homogeneous temperature distribution over the heated area of the hotplate (1–2% maximum temperature fluctuation). Temperature sensors, on- and off-membrane (near the circuitry), show an excellent thermal isolation between the heated membrane area and the circuitry-area on the bulk chip (chip temperature rises by max 6°C at 350°C membrane temperature). A logarithmic converter was included to measuring the SnO2resistance variation upon gas exposure over a range of four orders of magnitude. An Analog Hardware Description Language (AHDL) model of the membrane was developed to enable the simulations of the complete microsystem. Gas tests evidenced a detection limit below 1 ppm for carbon monoxide and below 100 ppm for methane.