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This article presents a novel fiber-optic-less 50-MHz single transformer isolated gate driver (GD) for medium voltage (MV) SiC mosfets. A unique edge-interval-OFF modulation scheme is proposed to allow signal and power simultaneously transmitted through a single transformer with minimal power switches and voltage sources. The proposed GD can also transmit the fault signal from the GD secondary side to primary side, eliminating the requirement for fiber-optic (FO) communication for fault feedback. The proposed GD offers a low propagation delay and can respond to short pulsewidths, as well as supports an ultra-wide duty-cycle range including 0% and 100% duty-cycle operation. Furthermore, it utilizes solid dielectrics to achieve a compact footprint of 61 mm × 24 mm × 30 mm and meet MV insulation requirements with a partial discharge (PD) inception voltage > 13.5 kVRMS under 60-Hz ac voltage and a PD-free operation under 100-kHz, 5-kV PWM voltage with a dv/dt of 100 V/ns. The proposed GD achieves an ultra-low coupling capacitance of 1.9 pF and a common-mode transient immunity (CMTI) > 100 V/ns, making it preferable to drive MV SiC mosfets with high dv/dt. The proposed GD eliminates the need for both FOs and bulky GD power supplies, resulting in a more than 10-fold reduction in size compared to conventional 10-kV isolated GDs and has the potential to be integrated into MV SiC device packages. Experimental results on 10-kV SiC mosfets validate the effectiveness of the proposed GD.

This letter presents a novel short-circuit protection (SCP) for medium-voltage (MV) SiC mosfets, that utilizes the turn-on dv/dt of SiC mosfet within a predetermined interval to monitor SC faults. Unlike conventional methods that detect the fault current/voltage magnitude, proposed turn-on dv/dt detection and protection timing sequence enable a very fast fault response time as well as enhance the noise immunity to fast switching of MV SiC mosfets. Furthermore, the proposed dv/dt sensing based SCP can be integrated with DESAT circuit to provide over-current protection under the fault-under-load condition. The proposed integrated implementation can respond to SC faults without the blanking-time limitation and eliminates the need for the extra high-voltage sensing capacitor to lower cost. Experimental results on 3.3-kV SiC mosfets are provided to validate the effectiveness of proposed SCP method.

Multilevel topologies with SiC devices for medium-voltage (MV) motor drive have advantages to reduce the harmonics and device voltage stress and increase efficiency. However, with the application of SiC devices, the reflected wave phenomenon still happens in multilevel motor drives due to its high dv/dt, resulting in overvoltage at motor terminals. This article proposed a T-type circuit-based active reflected wave canceller (ARWC) to suppress the overvoltage of an M-level motor drive with a reduced voltage rating of $V_{\mathrm {dc}}$ /( $M-1$ ). A coupled inductor is applied to isolate the ARWC output and the main inverter. In addition, the coupled inductor is designed with a small resistor to allow low current flow into ARWC. The proposed ARWC configuration can be applied for general multilevel topologies. A three-level ANPC converter with a 3.3-kV SiC device is built in the laboratory. A 1.2-kV SiC module is applied in the proposed ARWC. The experimental results at 1.6-kV $V_{\mathrm {dc}}$ and 16-A (rms) load current with and without proposed ARWC are provided and compared to verify the validity of the proposed method.

This article presents a self-voltage balanced three-level (3L) active-neutral-point-clamped (ANPC) medium-voltage (MV) inverter. Two switches of this inverter operate at high frequency (HF), while four switches operate at low frequency (LF), which is suitable to be implemented with hybrid “Si IGBTs + SiC MOSFETs” for MV applications. A 3.3-kV SiC MOSFET power module with low parasitic packaging is applied as HF switches, and the dc-link capacitor voltages can be self-balanced through periodic charging/discharging processes with a small decoupling capacitor. However, the inrush current occurs during voltage balancing processes, resulting in the false trigger of desat protection for LF switches. In this article, the mechanism of inrush current during voltage balancing processes is analyzed and a 3L gate driving method is proposed for LF switches to solve the false-triggering issue and improve the inrush energy loss distribution. In addition, high dv/dt of SiC switching transients may cause the false-triggering issue of HF switches, and desat protection design equations are therefore derived for this 3.3-kV SiC MOSFET power module to achieve a fast (< 440 ns) short-circuit response and maintain a good noise immunity to high dv/dt. A 4-kV dc, 40-kVA inverter prototype is built in the laboratory and the experimental results are provided to verify the proposed methods.

In order to suppress the input current distortion of critical conduction mode (CRM) boost power factor correction (PFC) converters, variable on-time (VOT) control has been adopted in many analog commercial integrated chips (ICs). However, the quantitative VOT expression applicable to analog control has not been studied until now. According to the fitting functional form of VOT, this paper proposes a uniform and simple VOT expression, which can be directly implemented by analog circuits and provide accurate VOT control just as digital control. Only an inverse signal of the rectified input voltage is additionally introduced to achieve accurate VOT control, and the inherent voltage feedback loop of PFC is utilized to eliminate the effect of the input rms voltage and output power. With the proposed quantitative design consideration, the optimum input current total harmonics distortion (THD) is naturally obtained without trial-and-error design. The experimental results of a 160-W prototype are built to verify the effectiveness and advantages of the proposed VOT control.