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This work presents a low noise active pixel sensor. It uses one additional transistor compared to standard 4T pixel to obtain 1/f noise reduction and high conversion gain. 1/f noise is reduced by periodically switching the in-pixel source follower between depletion and inversion. The depletion state is achieved by re-configuring the source follower into a MOS capacitor and depleting the channel by controlling the source-drain terminal. The state change of the in-pixel source follower also enhances the conversion gain. The test chip has a $64 \times 64$ pixel array with a $10~ {\mu }\text{m}$ pixel pitch fabricated in 350 nm AMS process. The measured integrated noise of a pixel in the frequency band 128 Hz to 50 KHz is $728~ {\mu V_{rms}}$ without switching. At a switching frequency of 4 MHz, the integrated noise reduces to $306~ {\mu V_{rms}}$ after switching resulting in a 7.5 dB reduction. The input referred noise is reduced from $26 {e_{rms}^{-}}$ to $7.3 {e_{rms}^{-}}$ after applying switching. When both, switching and conversion gain enhancement are applied, the input referred noise is further reduced to $2.3 {e_{rms}^{-}}$ with an enhanced conversion gain of $398\,\, {\mu V/e^{-}}$. [ABSTRACT FROM AUTHOR]

A low-power W-band gain-enhanced CMOS down-conversion mixer for millimeter-wave-to-baseband pulsed-radar receiver is presented. To enhance the equivalent load impedance while keeping the transconductance ($\text{g}_{\mathrm {m}}$) of the RF $\text{g}_{\mathrm {m}}$ stage unchanged and achieving prominent IF bandwidth, we propose a novel core IF load, which is based on the parallel combination of the cross-coupled PMOS transistors (CCPT) and the series RL circuit (i.e., CCPT-RL-based core IF load). The down-conversion mixer comprises a double-balanced Gilbert-cell-based mixer core with an inductive-peaking current-bleeding RF $\text{g}_{\mathrm {m}}$ stage and a CCPT-RL-based core IF load, two elliptic baluns, and a source follower buffer. Compared with the traditional down-conversion mixer for direct conversion receiver, conversion gain (CG), and noise figure (NF) can be significantly enhanced. For 88~100 GHz, the mixer consumes 5 mW and achieves excellent RF-port input reflection coefficient (${S}_{11}$) of −9.6~−19.1 dB and LO-port input reflection coefficient (${S}_{22}$) of −5.5~−21.9 dB. In addition, the mixer achieves excellent CG of 11.8~14.6 dB, NF of 14.2~15.2 dB, and LO-RF isolation of 34.6~35.3 dB–one of the best CG, NF, and LO-RF isolation results ever reported for a W-band down-conversion mixer. [ABSTRACT FROM AUTHOR]

In Part I of this paper, we introduce useful analysis that leads to a simple signal flow graph (SFG), which captures the FET-R-C circuit's action completely across a wide range of design parameters. Part I focuses on the analysis of a single-path FET-R-C circuit's signal transfer characteristics and gives us guidelines for sample-and-hold (S/H) and passive sampling mixer (P-M) designs. Part II extends the analysis to multi-path FET-R-C circuit configurations, e.g., a complex $I$-$Q$ passive mixer that is common in RF applications. Then the noise and driving-point impedance analyses are carried out to provide valuable insights of practical S/H and P-M designs. [ABSTRACT FROM AUTHOR]

A frequently occurring subcircuit consists of a loop of a resistor (R), a field-effect transistor (FET), and a capacitor (C). The FET acts as a switch, controlled at its gate terminal by a clock voltage. There may be many such identical circuits connected in parallel, each driven by a different phase of the clock. This subcircuit may be acting as a sample-and-hold (S/H), as a passive mixer (P-M), or as a bandpass filter or bandpass impedance. In this work, we will present a useful analysis that leads to a simple signal flow graph (SFG), which captures the FET-R-C circuit's action completely across a wide range of design parameters. The SFG dissects the circuit into three filtering functions and ideal sampling. This greatly simplifies analysis of frequency response, noise, input impedance, and conversion gain, and leads to guidelines for optimum design. The analysis is extended to multi-path realizations common in RF applications. Part I of this paper focuses on the analyses of a single-path FET-R-C circuit's signal transfer characteristics. Part II extends these analyses to multi-path FET-R-C circuit configurations, which is followed by the noise and driving-point impedance analyses. [ABSTRACT FROM AUTHOR]

A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP3 ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolations of better than 50 dB. The input second-order (IIP 2) and IIP 3 are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are then integrated with a differential low-noise amplifier (DLNA) and a poly-phase filter, to from a direct-conversion receiver (DCR). The DCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mW power consumption from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP2 and the IIP3 of the DCR are 33 dBm and -12 dBm, respectively. [ABSTRACT FROM PUBLISHER]

The performance of zero-IF receivers with current-driven passive mixers driven by 25% duty-cycle quadrature clocks is studied and analyzed. It is shown that, in general, these receivers outperform the ones that utilize passive mixers with 50% duty-cycle clocks. The known problems in receivers with 50% duty-cycle mixers, such as having unequal high- and low-side conversion gains, unexpected IIP2 and IIP3 numbers, and IQ crosstalk, are significantly lowered due to the operating principles of the 25% duty-cycle passive mixer. It is revealed that with an intelligent sizing of the design parameters, the 25%-duty-cycle-mixer-based receiver is superior in terms of linearity, noise, and elimination of IQ crosstalk. [ABSTRACT FROM PUBLISHER]