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In digital integrated circuits with multiple power domains, level shifters (LSs) are essential circuit elements that can transform the voltage region from low to high. However, high-frequency gate drivers can generate hundreds of voltages per nanosecond noise (high dV/dt noise). Such high dV/dt noise can cause malfunction of a conventional pulse-triggered cross-coupled LS (CCLS) that is used to control the high-side nMOS switch. In this article, a novel LS with noise immunity is proposed and investigated. Compared with the conventional resistor load LS, the proposed circuit adopts nMOS-R cross-coupled (NRCC) LS, and realizes the selective filtering ability by exploiting the path that filters out the noise introduced by the dV/dt. The high-voltage gate drive integrated circuit (HVIC) is implemented using a 600 V silicon-on-insulator (SOI) BCD process. Analyses and experiments show that the proposed design can help the HVIC maintain a high common-mode transient immunity (CMTI) of up to 137 V/ns while allowing a negative VS swing down to -9.4 V under a 15 V supply voltage. Compared with the traditional HVIC with resistance load LS, the proposed novel HVIC with the NRCC LS improves the noise immunity of dV/dt by 182%.

This article investigates the degradation mechanism in dV/dt noise immunity robustness of traditional resistive load level shifters (LSs) under total-ionizing-dose (TID) irradiation and proposes a novel radiation-hardened nMOS-R cross-coupled (NRCC) LS with dV/dt noise immunity. When TID irradiation induces threshold voltage drift and increases the off-state leakage current in power devices, the proposed circuit employs a differential and complementary structure to counteract the degradation of electrical performance in both branches caused by the TID irradiation, thereby achieving improved radiation-hardening performance. Measurement results demonstrate that the proposed high-voltage gate drive integrated circuit (HVIC) with the novel LS level exhibits 130-V/ns noise immunity at the irradiation dose of 100 krad(Si). A normalization method is used to process measurement results for visual comparison. The degradation of dV/dt noise immunity capability of the proposed LS is improved by 26.8%, 72.4%, and 94.9% compared with the traditional LS at the irradiation dose of 30, 50, and 100 krad(Si). The HVIC is implemented using a 600-V silicon-on-insulator (SOI) BCD process.

The total-ionizing-dose (TID) effect has different influences on bipolar junction transistors (BJTs), resistors, and MOSFETs, which leads to significant drifts in the overtemperature threshold in the traditional overtemperature protection circuit (OTPC). An OTPC with a dynamic comparison technique is proposed to improve the radiation-hardened capability. The proposed radiation-hardened OTPC employs two identical sensors to monitor the temperature and convert it into voltage for comparison to determine if overtemperature occurs. The voltage drifts caused by TID effects on two sensors vary dynamically and offset each other, so the overtemperature threshold will not drift theoretically. The normalization method is used to process measurement results to get a visual comparison. The measurement results show that the threshold drift of the proposed OTPC is 5.0% lower than that of traditional OTPC at 30 krad(Si), 7.1% lower at 50 krad(Si), and 10.3% lower at 100 krad(Si). Therefore, the proposed OTPC reduces the threshold voltage drifts effectively and has a good radiation-hardened effect.

This brief presents a novel over-temperature protection (OTP) technique with absolute OTP, dynamic OTP, and the thermal-restart function. Absolute OTP operates when the temperature of the power MOSFET reaches the junction temperature to avoid device breakdown. Dynamic OTP monitors the uneven thermal distribution on the chip. When the temperature difference between the power MOSFET and the controller is large, dynamic OTP is triggered to prevent the performance and lifetime degradation of devices. The chip restarts automatically after the temperature drops below the thermal hysteresis to reduce lifetime loss. Additionally, measurement results demonstrate that the current limitation situation results in the shutdown and the restart of the OTP. The overtemperature threshold and hysteresis of absolute OTP are 175°C and 15°C, dynamic OTP occurs when the temperature difference reaches 76°C, and the restart delayed time is 14.4 ms. The proposed dual over-temperature protection circuit with a thermal-restart function can avoid the damage caused by uneven thermal distributions on the chip, and further improve the reliability of the chip.

The total ionizing dose (TID) effect of low operation voltage MOSFET (LV-MOS), medium operation voltage lateral double-diffused metal–oxide–semiconductor field-effect transistor (MOSFET) (MV-LDMOS), and 600-V high operation voltage LDMOS (HV-LDMOS) manufactured by silicon-on-insulator (SOI) bipolar-complementary metal–oxide–semiconductor DMOS (BCD) process is investigated by experiments and 3-D TCAD numerical simulations, and the hardening technique is proposed and discussed. The experiment and simulation results of LV-MOS with three different structures indicate that the TID-induced leakage current is mainly caused by the STI oxide, which forms a leakage current path along the side of the channel region. The leakage current of LV-MOS with a square/ring shape gate (RG-MOS) structure does not increase even though the irradiation dose increases to 300 krad(Si). The RG-MOS structure can eliminate the TID-induced leakage current induced by segregating the channel from the STI region, which is used in MV-LDMOS and 600-V HV-LDMOS. The TID-induced leakage current of radiation-hardened MV-LDMOS does not increase at the irradiation dose of 300 krad(Si). The TID-induced leakage current of radiation-hardened 600-V HV-LDMOS is about four orders of magnitude less than that of standard 600-V HV-LDMOS at the irradiation dose of 50 krad(Si). The specific-on-resistance performance of MV-LDMOS and 600-V HV-LDMOS is improved with the increase of irradiation dose. The radiation-hardened technique used in this article can improve the TID tolerance of MOSFETs in SOI BCD process significantly. The systematic and thorough investigation of TID hardening technique of SOI BCD technology will contribute to the application of power ICs in the space environment.

In this article, the synergistic effect of negative gate bias and radiation on SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. Under negative gate bias (−5, −10, and −15 V), a slight decrease in the threshold voltage ( $V_{\mathrm {th}}$ ) of non-irradiated SiC MOSFETs is observed. The variation of trapped-oxide charge ( $N_{\mathrm {ot}}$ ) and SiC/SiO2 interface trap charge ( $N_{\mathrm {it}}$ ) can be obtained through the subthreshold swing and mid-gap voltage method. Although the $V_{\mathrm {th}}$ of non-irradiated SiC MOSFETs remains unchanged, significant increases in $N_{\mathrm {it}}$ and $N_{\mathrm {ot}}$ are observed due to the opposite effect of $N_{\mathrm {ot}}$ and $N_{\mathrm {it}}$ on $V_{\mathrm {th}}$ . This phenomenon is attributed to holes drifting to the interface and tunneling into the oxide layer under the negative gate bias. It is found through the $C_{\mathrm {g}}$ – $V_{\mathrm {gs}}$ characteristic curves that holes tunneling into the oxide layer are mostly from the channel region. For irradiated SiC MOSFETs, a large number of radiation-induced holes exist in the oxide layer above the channel region and JFET region, resulting in a decrease in $V_{\mathrm {th}}$ , which is mainly caused by an increase in $N_{\mathrm {ot}}$ .

Noise immunity is a critical index of high-voltage half-bridge gate driver integrated circuits (IC). Various noise cancelation technologies have been proposed to improve dv/dt noise immunity with sacrifices in terms of area and propagation delay time. Besides, when it is applied to an inductive load, the half-bridge driver is vulnerable to negative surges at the VS terminal, which is the offset ground of the high-side channel. A 300 V half-bridge gate driver IC with noise rejection module is designed in this paper. The noise immunity can be improved to 87.5 V/ns. The VS negative swing region can be extended to − 5.1 V. In addition, the proposed driver IC can work normally at a working frequency of 500 kHz and the delay matching time between the high-side and the low-side is less than 4 ns. The propagation delay time of the high-side channel is measured at 71.6 ns. Furthermore, gamma ray irradiation experimental results show that the proposed structure presents a good radiation tolerance of 100 krad (Si). The presented half-bridge gate driver IC is fabricated with the silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, which occupied an area of 1.86 mm2.

Nanoscale Ca(OH)2 particles as a novel cathode additive for nickel-based secondary batteries are synthesized by a homogeneous precipitation method. The influence of Ca(OH)2 additive on the electrochemical performance of two types of nickel electrode (using spherical Ni(OH)2 and g-CoOOH@Ni(OH)2) were evaluated. It is interestingly discovered that nano-Ca(OH)2 additives can efficiently improve the charge acceptance of both nickel electrodes. Especially, the charge acceptance of the 1.0 wt% nano-Ca(OH)2@g-CoOOH@Ni(OH)2 electrode at 70degC at 5C is over 90% and the discharge capacity can reach about 218 mAh g[?]1. These performance enhancements of nickel electrode mainly result from the combined coating with Ca(OH)2 and g-CoOOH. The modification of oxygen evolution reaction on the nickel electrode is primarily resulting from the use of Ca(OH)2 by increasing its potential and suppressing its rate. The observably lower charge transfer resistance of nickel electrode is mainly due to the high conductivity coating of g-CoOOH. Consequently, the proposed cathode additive is promising for the high-temperature property enhancement of nickel-based rechargeable batteries.

Nanoscale Ca(OH)2particles as a novel cathode additive for nickel-based secondary batteries are synthesized by a homogeneous precipitation method. The influence of Ca(OH)2additive on the electrochemical performance of two types of nickel electrode (using spherical Ni(OH)2and γ-CoOOH@Ni(OH)2) were evaluated. It is interestingly discovered that nano-Ca(OH)2additives can efficiently improve the charge acceptance of both nickel electrodes. Especially, the charge acceptance of the 1.0 wt% nano-Ca(OH)2@γ-CoOOH@Ni(OH)2electrode at 70°C at 5C is over 90% and the discharge capacity can reach about 218 mAh g−1. These performance enhancements of nickel electrode mainly result from the combined coating with Ca(OH)2and γ-CoOOH. The modification of oxygen evolution reaction on the nickel electrode is primarily resulting from the use of Ca(OH)2by increasing its potential and suppressing its rate. The observably lower charge transfer resistance of nickel electrode is mainly due to the high conductivity coating of γ-CoOOH. Consequently, the proposed cathode additive is promising for the high-temperature property enhancement of nickel-based rechargeable batteries.