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The current-voltage characteristics of Al+ implanted 4H-SiC p+n junctions show an important reduction of leakage currents with diode aging at room temperature. The case of a family of diodes that immediately after manufacture had forward current density increasing from 10-9 to 10-6 A/cm2 when biased from 0 and 2 V, and had a reverse leakage current density of @ 5×10-7 A/cm2 when biased at 100 V, is here presented and discussed. During diode manufacturing a post implantation annealing at 1600 °C for 30 min was followed by a 1000 °C 1 min treatment for metal contacts alloying. After 700 days of storage at room temperature, the diode reverse current density reached an asymptotical value of @ 4×10-11 A/cm2 that is four order of magnitude lower than the initial one. A 430 °C annealing that was made after 366 days is responsible of a decrease of one of these four orders of magnitude, but it does not interrupt the decreasing trend versus increasing time. This same annealing has been effective also for minimizing forward current for bias < 2 V, and sticking the diode turn-on voltage on 1.4 V and the current trend on an ideality factor of 2. These results show that in Al+ implanted 4H-SiC p+n junction there are defects that have an annihilation dynamic at very low temperatures, i.e. room temperature and 430 °C.

Post-implant annealing of Al implanted 4H-SiC has been performed in the temperature range from 1600°C to 1750°C. Annealing was conducted in a hot-wall CVD reactor using a silanerich ambient. Ar was used as the carrier gas to deliver the silane to the annealing zone where the sample was heated via RF induction. The resulting annealed surfaces exhibited a step-bunch free, smooth morphology when viewed on SEM and AFM. The maximum surface roughness as measured via AFM was 0.65 nm RMS for the sample annealed at 1750°C.

This work reports the realization and characterization of 4H-SiC p+/n diodes with the p+ anodes made by Al+ ion implantation at 400°C and post-implantation annealing in silane ambient in a cold-wall low-pressure CVD reactor. The Al depth profile was almost box shaped with a height of 6×1019 cm-3 and a depth of 160 nm. Implant anneals were performed in the temperature range from 1600°C to 1700°C. As the annealing temperature was increased, the silane flow rate was also increased. This annealing process yields a smooth surface with a roughness of the implanted area of 1.7 - 5.3 nm with increasing annealing temperature. The resistivity of the implanted layer, measured at room temperature, decreased for increasing annealing temperatures with a minimum value of 1.4 0-cm measured for the sample annealed at 1700°C. Considering only the current-voltage characteristic of a diode that could be modeled as an abrupt p/n junction within the frame of the Shockley theory, the diode process yield and the diode leakage current decreased, respectively, from 93% to 47% and from 2×10-7 Acm-2 to 1×10-8 Acm-2 at 100 V reverse bias, for increasing post implantation annealing temperature.

An n-type 8° off-axis <0001> 4H-SiC epitaxial wafer was processed. The n-type epilayer had doping and thickness of, respectively, ~3 × 1015 cm-3 and ~5 μm. p+/n diodes with not terminated junctions were constructed by a selective area implantation process of 9.2 × 1014 cm-2 Al+ ions at 400°C. The diodes had areas in the range 2×10-4 -1×10-3 cm2. The Al depth profile was 6×1019 cm-3 high and 164 nm thick. The post implantation annealing process was done in a high purity Ar ambient at 1600°C for 30 min. The diode current-voltage characteristics were measured in the temperature range 25-290°C. Statistics of 50-100 measurements per device type were done. The fraction of diodes that could be modeled as abrupt junctions within the frame of the Shockley theory decreased with increasing area value, but was always > 75%. The ideality factor was > 2 only at temperatures > 200°C and bias values < 1 V. The leakage current was extremely weak and remained of the order of 10-9 Acm-2 at 70°C and 500 V reverse bias. 4% of the diodes reached the theoretical voltage breakdown that was 1030 V. The surface roughness of un-implanted and implanted regions after diode processing was, respectively, 2 nm and 12 nm.

We report on the electrical characterization of Al+ implanted p+/n 4H-SiC diodes via a planar technology. Hot implantation at 400°C and post implantation annealing at 1600°C and 1650°C in high purity Argon ambient were done for the realization of p+/n diodes. The current voltage characteristics of the p+/n diodes and the resistivity of the implanted layer were measured at room temperature. The majority of the 136 measured diodes had a turn on voltage of 1.75 V for both annealing temperatures. The 1600°C annealed diodes showed an almost exponential forward characteristic with ideality factor equal to 1.4, an average reverse leakage current density equal to (4.8 ± 0.1)×10-9 A/cm2 at –100 V, and a break down voltage between 600 and 900V. The 1650°C annealed diodes often had forward “excess current component” that deviates from the ideal forward exponential trend. The average reverse leakage current density was equal to (2.7 ± 0.5)×10-8 A/cm2 at –100 V, and the breakdown voltage was between 700 and 1000V, i.e. it approached the theoretical value for the epitaxial 4H-SiC layer.

Al+ implanted p+/n 4H-SiC diodes were realized via planar technology. The p+/n junctions were obtained by hot implantation at 400°C, followed by a post implantation annealing at 1600°C in Silane ambient. 136 diodes and other test structures were measured: the current voltage^curves and the resistivity of the implanted layer were investigated at room temperature. The majority of the measured diodes had a turn on voltage of about 1.75 V, a forward characteristic with exponential trend and ideality factor equal to 1.2, and a very low spread in the distribution of the reverse leakage current values at –100V. The average reverse leakage current value is (9.7 ± 0.4) × 10-9 A/cm2. The breakdown voltage of these diodes approached the theoretical value for the use epitaxial 4H-SiC layer, i.e. 0.75 – 1.0 kV. All these positive results are penalized by the high resistivity value of the implanted Al+ layer, which amounts to 11 W·cm that is one order of magnitude higher than the desired value.

Varettoni: Janssen: Consultancy; Roche: Consultancy; ABBVIE: Other: travel expenses; Gilead: Other: travel expenses. Arcaini:Bayer, Celgene, Gilead Sciences, Roche, Sandoz, Janssen-Cilag, VERASTEM: Consultancy; Celgene: Speakers Bureau; Celgene, Roche, Janssen-Cilag, Gilead: Other: Travel expenses; Gilead Sciences: Research Funding.

Background. Non-chronic lymphocytic leukemia (non-CLL) clonal B-cell lymphocytosis (CBL) encompasses a heterogeneous group of hematologic disorders that are still poorly understood. The main purpose of this study was to explore the genomic landscape of non-CLL CBL, correlating the results with clinical, histological and immunogenetic features.