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The LESS signature scheme, introduced in 2020, represented a fresh start for code-based signatures. In this paper we explore advanced functionalities for signature schemes, stemming from the work of LESS. First, we adapt a recent protocol of Beullens et al.to obtain a construction for (linkable) ring signatures. Then, we realize an identity-based signature scheme following the traditional approach by Joye and Neven. Our performance numbers confirm that signature schemes based on the code equivalence problem have considerable potential for practical applications.

The significant effort in the research and design of large-scale quantum computers has spurred a transition to post-quantum cryptographic primitives worldwide. The post-quantum cryptographic primitive standardization effort led by the US NIST has recently selected the asymmetric encryption primitive Kyber as its candidate for standardization and indicated NTRU, as a valid alternative if intellectual property issues are not solved. Finally, a more conservative alternative to NTRU, NTRUPrime was also considered as an alternate candidate, due to its design choices that remove the possibility for a large set of attacks preemptively. All the aforementioned asymmetric primitives provide good performances, and are prime choices to provide IoT devices with post-quantum confidentiality services. In this work, we present a comprehensive exploration of hardware designs for the computation of polynomial multiplications, the workhorse operation in all the aforementioned cryptosystems, with a thorough analysis of performance, compactness and efficiency. The presented designs cope with the differences in the arithmetics of polynomial rings employed by distinct cryptosystems, benefiting from configurations and optimizations that are applicable at synthesis time and/or run time. In this context, we target a use case scenario where long-term key pairs are used, such as the ones for VPNs (e.g., over IPSec), secure shell protocols and instant messaging applications. Our high-performance design variants exhibit figures of latency comparable to the ones needed for the execution of the symmetric cryptographic primitives also included in the Post-Quantum schemes. Notably, the performance figures of the designs proposed for NTRU and NTRU Prime surpass the ones described in the related literature.

Side-channel attacks are a prominent threat to the security of embedded systems. To perform them, an adversary evaluates the goodness of fit of a set of key-dependent power consumption models to a collection of side-channel measurements taken from an actual device, identifying the secret key value as the one yielding the best-fitting model. In this work, we analyze for the first time the microarchitectural components of a 32-bit in-order RISC CPU, showing which one of them is accountable for unexpected side-channel information leakage. We classify the leakage sources, identifying the data serialization points in the microarchitecture and providing a set of hints that can be fruitfully exploited to generate implementations resistant against side-channel attacks, either writing or generating proper assembly code.

The vast diffusion of microcontrollers has led to their employment in security sensitive contexts, where the need for trusted implementations of cryptographic algorithms is paramount. These architectures are usually endowed with software and occasionally hardware implementation of ciphers, but in both cases, the price envelope is the first figure to be optimised. The strongest threat to microcontroller security has been proven to be represented by side-channel attacks: power consumption analysis and Electromagnetic (EM) emissions analysis being the prime opportunities to retrieve the secret key embedded in the devices via commonly overlooked information leakage. We propose an efficient solution to the problem of compromising EM emissions from an embedded device, showing which are the design space parameters available to the designer, and how to appropriately tune the security margin with respect to the performances, obtaining an order of magnitude improvement over the state-of-the-art solutions.

The vasculature is innervated by a network of peripheral afferents that sense and regulate blood flow. Here, we describe a system of non-peptidergic sensory neurons with cell bodies in the spinal ganglia that regulate vascular tone in the distal arteries. We identify a population of mechanosensitive neurons, marked by tropomyosin receptor kinase C (TrkC) and tyrosine hydroxylase in the dorsal root ganglia, which projects to blood vessels. Local stimulation of TrkC neurons decreases vessel diameter and blood flow, whereas systemic activation increases systolic blood pressure and heart rate variability via the sympathetic nervous system. Ablation of the neurons provokes variability in local blood flow, leading to a reduction in systolic blood pressure, increased heart rate variability, and ultimately lethality within 48 h. Thus, a population of TrkC+sensory neurons forms part of a sensory-feedback mechanism that maintains cardiovascular homeostasis through the autonomic nervous system.