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This paper presents a filtering power amplifier (PA) with wide bandwidth. A bandpass filter (BPF) using discriminating coupling is first proposed to be utilized as the output matching network (OMN) of PA. Discriminating coupling means that the fundamental and the harmonics of the proposed structure have different coupling coefficients. Thus, the input impedances of the fundamental, second and third harmonics could meet the requirements of the extended continuous mode theory, respectively. Also, good frequency selectivity is obtained. The working principle of discriminating coupling, the filter synthesis theory and the equivalent circuit are utilized to guide the design of the filtering PA. To demonstrate the proposed structure, a compact filtering PA operating at 1.8 GHz is designed. The measured results exhibit good frequency selectivity and high power added efficiency (PAE). More importantly, comparing to the previous filtering power amplifiers (PAs) with good frequency selectivity, the proposed design possesses wide bandwidth of 31.1% with PAE higher than 60%. [ABSTRACT FROM AUTHOR]

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

Clock skew and component mismatches in continuous-time DACs introduce two types of error: static error and dynamic error. Both types of error typically limit the performance of practical, high-resolution, and continuous-time DACs, but most prior calibration techniques primarily reduce only static error. An exception is a recently published mismatch noise cancellation (MNC) technique that adaptively measures and cancels both types of error over the DAC’s first Nyquist band. However, a disadvantage of the technique is that it requires an oversampling ADC that operates at several times the DAC’s Nyquist rate to prevent convergence error that would otherwise be caused by aliasing. This paper presents a sub-sampling version of the MNC technique that avoids this limitation at the expense of a lower calibration convergence rate. As proven in the paper, the subsampling MNC technique allows aliasing to occur, but in such a way that convergence error is avoided. [ABSTRACT FROM AUTHOR]

This paper analyzes the ability to suppress in-band noise power of a regenerative amplifier (RA) operating in the nonlinear regime in response to a continuous wave (CW) input tone. As opposed to the linear regime where a CW tone and the noise floor experience the same transfer function, it is shown that the non-linear saturation behavior of an RA yields different transfer characteristics between a CW tone and noise, ultimately leading to an improvement in the output carrier-to-noise ratio (CNR). This is all thanks to the high gain, narrow bandwidth, and the compressive third-order nonlinearity of the RA. This non-linear noise suppression is first analyzed mathematically using single tones in the frequency domain to represent the signal and the noise. Then, simulation of an RA circuit model is shown to be in excellent agreement with the analytical results. Lastly, a discrete RA has been implemented to experimentally verify the noise-suppression phenomenon. The measurement results clearly demonstrate noise suppression and show an output CNR improvement of up to 3 dB. Potential applications of the RA with noise suppression are also discussed. [ABSTRACT FROM AUTHOR]

Inadvertent but inevitable mismatches among nominally identical unit element 1-bit digital-to-analog converters (DACs) within a multi-bit Nyquist-rate DAC cause both static and dynamic error in the DAC’s continuous-time output waveform. Prior calibration techniques are able to suppress static mismatch error, but have had limited success in suppressing dynamic mismatch error. This paper presents a digital calibration technique that adaptively measures and cancels both static and dynamic mismatch error over the DAC’s first Nyquist band. The technique is capable of either foreground or background operation, and is relatively insensitive to non-ideal circuit behavior. The paper presents a rigorous mathematical analysis of the technique, and demonstrates the results of the paper with both behavioral and transistor-level circuit simulations. [ABSTRACT FROM PUBLISHER]

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50- $\Omega $ load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs. [ABSTRACT FROM AUTHOR]

As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself. [ABSTRACT FROM AUTHOR]

This paper proposes a power-efficient and memory-optimized FPGA-based solution for the memory and compute-intense re-gridding process used in implementing Non-uniform Fast Fourier Transform (NuFFT) algorithm. Re-gridding refers to mapping non-equispaced sampled data onto a uniform grid using an interpolation kernel function. Re-gridding is the most time-consuming step in the entire NuFFT computation. The proposed solution is based on better utilization of FPGA resources and minimizing the number of accesses to the external memory. We demonstrate high performance over a wide range of configurations and data-sizes. This paper targets a generic solution to arbitrary sampling trajectories and gives trajectory specific solutions for some well-known trajectories in NuFFT applications, such as magnetic resonance imaging and synthetic aperture radar. Compared with existing solutions, throughput is improved by over 9.6 when compared with the existing FPGA-based techniques, whereas computational power efficiency (in terms of MFLOPS/Watt) is improved by over 15 times. Compared with GPU-based technique, 9.59 times higher MFLOPS per watts are achieved. The proposed architecture is implemented using hardware description language as well as high-level synthesis (HLS)-based OpenCL framework and the comparison is reported. Hence, this paper also serves as a reference for the comparison of HLS-based solutions against optimized HDLs. Accuracy of the re-gridding process is also reported in terms of signal-to-noise ratio. [ABSTRACT FROM AUTHOR]

In this paper, we show that amplitude transitions that are inherent to the multilevel outphasing radio transmitter architecture distort the transmitted signal due to time-domain discontinuities. In order to address this challenge, we propose a new transmitter architecture called tri-phasing which avoids discontinuities in signal waveforms and thus achieves significantly better linearity than multilevel outphasing. The output waveform in tri-phasing can be made continuous by representing the baseband signal with three components. One of the three components is amplified by discrete amplitude steps, whereas the other two are used to compensate the instantaneous shift in the output waveform due to the discrete amplitude step and to provide fine amplitude resolution. An implementation of the tri-phasing transmitter requires three phase modulators and additional digital signal processing. The system-level simulations performed in this paper demonstrate that the ACLR of a multilevel outphasing transmitter with 4 amplitude levels and 10-bit phase resolution is limited to −48 dBc, when simulated with a 100 MHz carrier-aggregated LTE downlink signal at 2.46 GHz carrier frequency. The proposed tri-phasing transmitter achieves −58 dBc ACLR with the same simulation parameters, indicating that continuous amplitude transitions can significantly improve the transmitter linearity. [ABSTRACT FROM AUTHOR]

This paper proposes a technique which allows quadband impedance matching and impedance level shifting Doherty power amplifier (DPA) design. By using novel coupler networks with reactance and choosing appropriate complex load impedances, the quadband DPA can reach a power back-off range (OBO) of over 9 dB. In addition, the peak PA branch and the carrier PA branch use different coupler network parameters in order to satisfy different impedance requirements. To illustrate the design procedure a quadband DPA with 9 dB OBO operating in 0.5-0.7 GHz, 1.5-1.7 GHz, 2.5-2.7 GHz, and 3.5-3.7 GHz frequency ranges is designed, fabricated and tested. Measurements demonstrate that the DPA can deliver saturated output power between 43.1 dBm and 43.8 dBm in all four bands, with a drain efficiency ranging from 63.3% to 66.5%. Also, drain efficiency of from 42.2% to 52.3 % can be obtained at an OBO of 9 dB level. The DPA implemented here shows state-of-the-art performance for OBO under quad-band operation. [ABSTRACT FROM AUTHOR]

This paper presents a foreground calibration method for both a sampler and a track-and-hold (T/H) buffer bandwidth mismatch in highly time-interleaved analog-to-digital converters (TI-ADCs). The T/H buffer bandwidth mismatch stems from the length difference of interconnect lines between the buffer and the channel ADC, while the sampler bandwidth mismatch arises from the mismatch in a switch and a sampling capacitor. To address both mismatches along with other mismatches residing in TI-ADCs, this papers utilizes least-squares (LS) minimization technique in order to extract mismatch parameters while injecting a sinewave at two distinct frequencies. Programmable capacitor arrays (PCAs) are used to tune the bandwidth of sampler, and correcting buffer bandwidth mismatch is performed in digital-domain. The method presented here is scalable to arbitrary number of interleaved paths, and can easily be combined with existing calibration methods for gain, offset, and timing-skew mismatches. Numerical experiment via Monte-Carlo simulations demonstrates significant performance improvement in the spurious-free dynamic range (SFDR) from 38 dB to 75 dB for a 32-channel time-interleaved ADC model that includes all major mismatches. [ABSTRACT FROM PUBLISHER]

This paper presents a digitally programmable bi-directional 7-bit passive phase shifter in a 65 nm CMOS technology. The core of this passive vector-synthesized phase shifter is a hybrid quadrature generator (HQG), an interstage matching network, and a passive vector modulator (PVM). This work proposes a high coupling-factor-based quadrature generator design methodology and demonstrates it with a compact vertical transformer. The interstage matching network between HQG and PVM is proposed to release the bandwidth bottleneck and achieve a 34% fractional frequency bandwidth. Two 6-bit X-type attenuators in the I and Q path form a high-resolution 12-bit controlling word. In 32–40 GHz, this 7-bit 360° phase shifter achieves a measured 2.8° step with 0.45-1.6° RMS phase error and 0.2-0.36 dB RMS magnitude error. With the broadband technique, its 3-dB bandwidth reaches 30.2-42.7 GHz with a 2.8° RMS phase error. Its in-band 1-dB compression point is 10.2 dBm. With the proposed compact HQG and PVM, this mm-wave passive phase shifter only occupies $220\times 630\,\,\mu \text{m}^{2}$ and has no power consumption. [ABSTRACT FROM AUTHOR]

Cartesian feedback (CF) linearization for radio amplifiers is appealingly simple, but it imposes a trade-off between signal bandwidth and feedback delay. In almost all of the CF literature, it is a first-order circuit. In this paper, we examine two second-order CF linearizers and show that they can provide deeper suppression of intermodulation distortion or greater signal bandwidth at a given loop delay. Twin-loop CF with damping factor 0.707, for example, can provide 20 dB lower intermodulation distortion and half the error vector magnitude (EVM), relative to first-order CF. For twin-loop CF and proportional-integrator CF, we provide the first analyses of their behavior, stability limits, and linearization performance. Comparison with simulations using nonlinear amplifier models shows both the value and the shortcomings of linear analysis. Our new spectral separation approach leads to insights about linearization and EVM. [ABSTRACT FROM AUTHOR]

Constrained by the transimpedance limit, the conventional 1-stage shunt-feedback transimpedance amplifier (1S-SF-TIA) suffers poor noise and gain at higher data rates. In this paper, we propose to use a multi-stage stagger-tuned amplifier (MSTA) to constitute TIA (MSTA-TIA), which not only transcends the transimpedance limit of 1S-SF-TIA, but also realizes noise reduction in multiple fronts. First, the high-gain MSTA enables 17X TIA gain over 1S-SF-TIA, which effectively suppresses the white noise. Second, the MSTA realizes at least 2.8X~1.6 lower noise than the conventional multi-stage amplifier, which is essential to form low-noise TIA since the amplifier noise usually dominates. Third, the TIA built upon the 3-stage STA also shows steeper out-of-band roll-off to enable high-frequency noise reduction. Overall, the MSTA-TIA achieves 6.9X and 1.9X noise power reduction over conventional single-stage and multi-stage SF-TIAs. As a demonstration, a 10 Gb/s optical receiver front-end prototype employing proposed MSTA-TIA topology is implemented in a standard $0.18~\mu \text{m}$ CMOS technology. It achieves transimpedance gain of 68.3dB $\Omega $ , electrical bandwidth of 8.5GHz, and excellent input-referred noise current of $0.97~\mu $ Arms. The chip occupies 0.78 mm2 while consuming 43 mA from 1.8 V power supply. The low-noise design methodology in this paper empowers mature CMOS to compete with SiGe to make low-noise high-gain optical IC. [ABSTRACT FROM AUTHOR]

This paper implements a wide aperture high-resolution true time delay for frequency-uniform beamforming gain in large-scale phased arrays. We propose a baseband discrete-time delay-compensating technique to augment the conventional phase-shift-based analog or hybrid beamformers. A generalized design methodology is first developed to compare delay-compensating analog or hybrid beamforming architecture with their digital counterpart for a given number of antenna elements, modulation bandwidth, ADC dynamic range, and delay resolution. This paper shows that delay-compensating analog or hybrid beamformers are more energy-efficient for high dynamic-range applications compared to true-time-delay digital beamformers. To demonstrate the feasibility of our proposed technique, a four-element analog delay-compensating baseband beamformer in 65-nm CMOS is prototyped. A time-interleaved switched-capacitor array implements the discrete-time delay-compensating beamformer with a wide delay range of 15-ns and 5-ps resolution. Measured power consumption is 47 mW with frequency-uniform array gain over 100-MHz modulated bandwidth, independent of angle of arrival. The proposed delay compensation scheme is scalable to accommodate the delay differences for large antenna arrays with higher range/resolution ENOB compared with prior art. [ABSTRACT FROM AUTHOR]

This paper presents a highly linear BiCMOS sample and hold amplifier (SHA) providing 2.8-GS/s intermediate frequency (IF) sampling for a 1-GHz input bandwidth spanning from 1.5 to 2.5 GHz. A single-transistor hold-mode feedthrough cancellation technique is implemented to remove distortion resulting from the nonlinear parasitic capacitance at the sampling node. The SHA is designed in a mainstream 130-nm BiCMOS technology using SiGe heterojunction bipolar transistors to buffer and sample the wideband input. The proposed SHA enables monolithic integration with a high-speed analog-to-digital converter core to realize a high-performance converter solution. This independent sampling front end occupies a core chip area of 0.6 mm2 and consumes an average power of 1.26 W. The SHA is a pseudo-differential open-loop design that includes two cascaded track-and-hold amplifiers, a high-speed clock driver, and externally adjustable current mirror biases. The high-speed clock drivers and buffers add 170 mW to the total power consumption. The measurements of the fabricated SHA show a 10-bit effective resolution across the 1-GHz IF bandwidth and < −61-dBc HD2 and HD3. [ABSTRACT FROM AUTHOR]

Pulse compression (PuC) is exploited in several applications, where the impulse response of a linear system must be estimated in a noisy environment. In nondestructive testing (NDT), PuC based on frequency-modulated signals is applied with sensors of different types. The presence of sidelobes in the impulse response retrieved after the PuC is a major drawback of the method as it degrades the quality of the estimation. To limit this effect, the matched filter is usually shaped by means of windows. Here, a windowing function based on reactance transformation is proposed that outperforms the most used ones in terms of near-sidelobes level reduction and sidelobes oscillations suppression. Numerical and experimental data were used to validate the technique. It is shown that the proposed approach is particularly suitable for those NDT techniques, such as eddy current and thermography that use very broadband excitations. The proposed window function is first introduced and applied to linear frequency-modulated signals and then extended to nonlinear frequency-modulated signals, which are needed in some applications. The quite general framework introduced in this paper for designing frequency-modulated signals and optimizing sidelobes is of general validity and can be successfully exploited in any application relying on chirp PuC. [ABSTRACT FROM AUTHOR]

Walsh-Hadamard based orthogonal sampling of signals is studied in this paper, and an application of this technique is presented. Using orthogonal sampling, a single analog-to-digital converter (ADC) only is sufficient to perform parallel (simultaneous) recording from the sensors. Furthermore, employing Walsh functions as modulation signals, the required bandwidth of the ADC in the proposed system is equal to the bandwidth of a time-multiplexed ADC in a system with identical number of recording channels. Therefore, the bandwidth of the ADC in the proposed system is effectively employed and shared among all the channels. The efficient usage of the ADC bandwidth leads to saving power at the ADC stage and reducing the data-rate of the output signal compared to state-of-the-art recording systems based on frequency-division multiplexing. This paper presents the orthogonal sampling technique for neural recording in multi-channel recording systems which is implemented with four recording channels using a $0.18~\mu \text{m}$ technology which results in a power consumption of $1.26~\mu \text{W}$ /channel at a 0.8 V supply. [ABSTRACT FROM AUTHOR]

A design methodology for making magnetic coupling wireless power transfer (MC-WPT) systems resonate at given frequencies is proposed in this paper. Proposing such a method not only can improve the energy efficiency against frequency splitting, but also can satisfy the requirement of frequency standards and then promote its industrial application. The method is based on eigenvalues configuration and comprehensively considers all electric parameters. The quantitative relationship between the performance indexes and electric parameters is derived, based on which the expected electric parameters can be quickly and accurately determined. The design theory and design flow are provided, and practical systems are designed, simulated and measured to show the effectiveness of the proposed method. The results show that the proposed method can: 1) eliminate frequency splitting to make MC-WPT systems resonate at a given frequency; 2) utilize frequency splitting to make MC-WPT systems resonate at two given frequencies. [ABSTRACT FROM AUTHOR]

In this paper, we present an integrator-differentiator transimpedance amplifier (I-D-TIA) with a dc compensation, which incorporates widely tunable multi-element pseudo-resistors (MEPRs) in its dc servo loop and ac signal path. The implemented MEPR in the dc path is continuously tunable from $460 \,\mathrm {k\Omega }$ to $300 \,\mathrm {G\Omega }$ allowing the TIA to process dc currents with a dynamic range of more than $100 \,\mathrm {dB}$. The MEPR in the differentiator ac signal path provides a tunable resistance between $0.3 \,\mathrm {M\Omega }$ and $100 \,\mathrm {M\Omega }$ , resulting in an overall ac transimpedance between $3 \,\mathrm {M\Omega }$ and $1 \,\mathrm {G\Omega }$. For the lowest ac transimpedance, a bandwidth of $10 \,\mathrm {MHz}$ is achieved. The TIA provides a minimum input-referred current noise density of $1.6\,\mathrm {fA}/\mathrm {\sqrt {Hz}}$. The implemented MEPR has been optimized regarding its high-frequency noise by minimizing its parasitic capacitances. The MEPR shows an inherent shot noise suppression such that its noise stays close to the theoretical thermal noise limit and significantly below the theoretical shot noise limit, even for large dc currents. By using a sub-VSS supply for the MEPR, the asymmetry in its output characteristic is greatly reduced, leading to a linear signal swing of $1.5\,\mathrm {V_{pp}}$ with a THD below $1 \mathrm {\%}$ on a $1.8-\mathrm {V}$ supply. Thanks to this high linearity, large bandwidth, and high dc current dynamic range, the proposed TIA can be used in a wide variety of applications from high-sensitivity, low-bandwidth lock-in detection to transient current sensing with sub-microsecond timing resolutions. [ABSTRACT FROM AUTHOR]

In this paper, a new effective approach is proposed to design compact multifunctional reconfigurable filtering power divider (FPD) based on a developed tunable multi-mode FPD topology. Different from conventional tunable FPD method by cascading tunable filter with power divider (PD), and double tunable filtering structures based on the tunable FPD method, it provides one promising solution of high operation performance, miniaturization and design flexibility enhancement etc., for industrial multi-functional modern wireless communication systems. By reformulating the traditional coupling matrix in terms of element-variable coupling coefficients for the developed tunable FPD topology, bandwidth (BW), center frequency (CF), as well as power division ratio (PDR) tuning are well accounted, which can help guide a new class of tunable FPD designs. For demonstration, a new second-order tunable FPD with only one common ring loaded coupled line tunable resonant unit is implemented as an example without losing generality. Higher-order tunable FPD case is further discussed and investigated by freely generalizing the FPD structure through the adoption of different tunable resonant units without dramatically increasing circuit complexity and size. Experimental results indicates that an improved performance (wider tuning range for CF, BW and PDR with nice isolation and matching), a very compact size and flexible design are achieved in the proposed work, which stands out from those in the literature. [ABSTRACT FROM AUTHOR]

A novel all-digital phase-locked loop (ADPLL) for fast and high-linear FMCW signal generation is presented in this paper. Fast chirp slope is enabled by two-point modulation (TPM) technique and ramp linearity distortion induced by digitally- controlled oscillator (DCO) is suppressed by wide loop bandwidth. A calibration-free retiming fractional frequency dividing (FFD) scheme based on digital phase interpolator (DPI) is proposed to suppress the $\Delta \Sigma $ quantization noise and break the loop bandwidth limitation. A parasitic insensitive DPI is utilized in the retiming FFD scheme to achieve high-linear phase interpolation. A high frequency resolution DCO with 9.8-kHz/bit least significant bit (LSB) and a vernier time-to-digital convertor (TDC) with 2.3-ps time resolution are employed to further minimize the quantization noise. Implemented in 40-nm CMOS, the ADPLL prototype consumes 33.8 mW power and 0.32 mm2 chip area. Measurement results show that 78 MHz/ $\mu \text{s}$ maximum chirp slope is achieved with 167 kHz root-mean-square (RMS) frequency error. The minimum RMS frequency error is only 5.6 kHz when 300 MHz frequency is swept in 1 ms. The phase noise from 12.15 GHz carrier is −113.6 dBc/Hz at 1-MHz offset. [ABSTRACT FROM AUTHOR]

This paper presents a multi-mode, dynamically zooming analog to digital converter (ADC). The architecture is based on a 5b interpolating flash ADC as the zooming unit and a passive discrete-time $\Delta \Sigma $ modulator as the fine conversion unit. The proposed ADC provides a dynamic zooming technique, employing an interpolating zooming front-end. The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it suitable for cellular applications including 4G radio systems. By reconfiguring the OSR, bias current, and component parameters, optimal power consumption can be achieved for every mode. The ADC is implemented in $0.13~\mu \text{m}$ CMOS technology and it achieves an SNDR of 83/75.7/73.2/67 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/4.7/8.1/10.3mW power consumption from a 1.2 V supply. [ABSTRACT FROM AUTHOR]

This paper presents a systematic procedure that can be used to create operational transconductance amplifiers (OTAs) for closed-loop operation using multiple low-gain stages to realize extremely high DC gain. Such devices are necessary to realize analog functions with demanding absolute accuracy requirements, e.g., high-resolution ADCs and DACs. The principle is based on the cascade of undamped integrators to realize large DC gains and a state-space derived controller to stabilize its operation in a closed-loop configuration. A programmable OTA fabricated in the IBM 130 nm CMOS process is used as a test vehicle to prove the design principle through its 2 to 5th-order realization. Measured data reveals DC gains ranging from 50 to 150 dB with a 3-dB bandwidth of 10 kHz and a unity gain frequency of 10 MHz. While this paper demonstrates the design principles using CMOS integrated circuits, the principle is general and can be applied to any type of circuit technology in integrated or discrete implementation. Moreover, the methods are easily automated as the principles are based on closed-form formulae as opposed to iterative numerical search techniques. [ABSTRACT FROM PUBLISHER]

This paper presents the analysis and design of a novel broadband low-noise amplifier (LNA) with larger than seven-octave bandwidth. To achieve good impedance matching, flat gain, and low noise over larger than seven-octave bandwidth, the combination technique of shunt-resistive feedback, dual inductive-peaking techniques as well as a compact improved active load supporting broadband RF biasing from dc to 20 GHz, is proposed for LNA design. The gain and noise improvement principles of the proposed technique are also analyzed theoretically. Based on the theoretical study, a three-stage LNA with larger than seven-octave bandwidth, i.e. 0.1 to 20 GHz, is designed and verified using a 0.15- $\mu \text{m}$ GaAs pHEMT technology. The LNA experimental results show a high gain of 28.6 dB, good noise figure of 3.1 to 5.8 dB, and output $P_{\mathrm {-1\,\,dB}}$ of 7.8 to 12.7 dBm over the broad frequency range of 0.1 to 20 GHz. The proposed LNA has a compact chip size of only 1.53 mm2 including testing input/output pads. [ABSTRACT FROM AUTHOR]

An area-efficient low-power fully integrated output-capacitorless low-dropout regulator (OCL-LDO) is presented in this paper. The three-stage OCL-LDO utilizes an embedded differentiator-based active zero compensation technique together with adaptive biasing. The proposed active zero compensation helps enhance the unity-gain bandwidth (UGB) of the regulator with very small silicon area and almost no extra current consumption. The UGB is therefore able to be maintained above 2.5 MHz even at a measured quiescent current of mere $1.6~\mu \text{A}$. Adaptive bias is employed to further stabilize the circuit and extend the bandwidth extension as well as enhance the transient response. The chip area is 0.0021 mm2 with maximum load capability of 25 mA, which leads to a maximum current density of 11.9 A/mm2. The measured voltage spikes are below 40 mV for full-load transient responses, and the response time is about 1.2 ns. The voltage spikes of line transient responses are only 4 mV at full load. The measured full-load power-supply rejection is better than −44 dB up to 100 kHz. [ABSTRACT FROM AUTHOR]

This paper presents a PLL supporting diverse low-power clocking needs including wide input (6–200 MHz) and output (0.15–5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high −3dB PLL bandwidth (>40% of $f_{\mathrm{ REF}}=19.2$ MHz), and the proposed reference current generator (IrefGen) provides accurate current with <4% tolerance without the need for external components or on-chip precision resistors. IrefGen decouples PLL loop dynamics from feedback divide ratio and provides immunity to systematic capacitor variation. Power gating of switched-cap loop filter’s bias circuits results in more than 10% PLL total power savings. The PLL achieves 1.6-ps integrated RMS jitter at 4 GHz using 100-MHz reference while consuming 2.6 mW from 0.95 V. The PLL performance satisfies the stringent PCIe Gen2/3 jitter specifications without resorting to inductors. [ABSTRACT FROM AUTHOR]

This paper presents a transformer-based 3-dB differential coupler, which features the suppression of both common-mode and cross-mode signals. Transformer is utilized rather than the quarter-/half-wavelength lines, and the circuit size can be significantly reduced. The bandwidth of the proposed differential coupler can be enhanced by increasing the coupling coefficient of the transformer. For the proof of concept, the proposed transformer-based 3-dB differential coupler is implemented on the substrate integrated suspended line (SISL) platform. Well agreed simulated and measured results verified the feasibility of the proposed differential coupler. From 0.4 to 0.6 GHz, the measured common-mode suppression is better than 10 dB with a maximum 30 dB, and the measured cross-mode suppression is better than 30 dB. Compared with the previous designs, the self-packaged SISL differential coupler has a much smaller size of $0.08 \lambda _{0} \times 0.08\lambda _{0}$. The proposed design methodology has advantages of compact size, suppression of both common-mode and cross-mode signals, and controllable bandwidth. [ABSTRACT FROM AUTHOR]

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth-order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure-of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst additionally offering direct integration with digital systems. [ABSTRACT FROM AUTHOR]

For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1st-order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account. [ABSTRACT FROM AUTHOR]

This paper presents a time-interleaved analog-to-digital converter mismatch calibration, which can be adapted to any interleaving factor and calibrate offset, gain, time skew and bandwidth mismatches. Moreover, the proposed scheme utilizes a non-return-to-zero pilot signal, avoiding the high-resolution requirements of sinusoidal generators. In addition, there are no multiplications in the detection path in contrast with the state-of-the-art approaches. Consequently, the proposed calibration presents the smallest complexity in terms of hardware requirements compared to previous work (to the author’s knowledge). Therefore, the proposed calibration can be made with the smallest area and power consumption. Numerical simulations show an SNDR improvement of 49.52 dB for a 12-bit 4-channel TI-ADC and an SNDR improvement of 29.64 dB for an 8-bit 32-channel TI-ADC when random mismatches are applied. The measurement results show an SNDR improvement of 24.68 dB for a 3.6 GS/s 2-channel TI-ADC experimental board. [ABSTRACT FROM AUTHOR]

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36%, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate $< 1\text{E}$ -10 with a power efficiency of 4.75 pJ/bit. [ABSTRACT FROM AUTHOR]

This paper considers two-rate based structures for variable fractional-delay (VFD) finite-length impulse response (FIR) filters. They are single-rate structures but derived through a two-rate approach. The basic structure considered hitherto utilizes a regular half-band (HB) linear-phase filter and the Farrow structure with linear-phase subfilters. Especially for wide-band specifications, this structure is computationally efficient because most of the overall arithmetic complexity is due to the HB filter which is common to all Farrow-structure subfilters. This paper extends and generalizes existing results. Firstly, frequency-response masking (FRM) HB filters are utilized which offer further complexity reductions. Secondly, both linear-phase and low-delay subfilters are treated and combined which offers trade-offs between the complexity, delay, and magnitude response overshoot which is typical for low-delay filters. Thirdly, the HB filter is replaced by a general filter which enables additional frequency-response constraints in the upper frequency band which normally is treated as a don't-care band. Wide-band design examples (90, 95, and 98% of the Nyquist band) reveal arithmetic complexity savings between some 20 and 85% compared with other structures, including infinite-length impulse response structures. Hence, the VFD filter structures proposed in this paper exhibit the lowest arithmetic complexity among all hitherto published VFD filter structures. [ABSTRACT FROM AUTHOR]

This paper introduces reconfigurable nonuniform transmultiplexers (TMUXs) based on fixed uniform modulated filter banks (FBs). The TMUXs use parallel processing where polyphase components, of any user, are processed by a number of synthesis FB and analysis FB branches. One branch represents one granularity band, and any user can occupy integer multiples of a granularity band. The proposed TMUX also requires adjustable commutators so that any user occupies any portion of the frequency spectrum. The location and width of this portion can be modified without additional arithmetic complexity or filter redesign. This paper considers both cosine modulated and modified discrete Fourier transform FBs. It discusses the filter design, TMUX realization, and the parameter selection. It is shown that one can indeed decrease the arithmetic complexity by proper choice of system parameters. For the critically sampled case and if the number of channels is higher than necessary, we can reduce the arithmetic complexity. In case of an oversampled system, the arithmetic complexity can be reduced by proper choice of the number of channels and the roll-off factor of the prototype filter. The proposed TMUX is compared to existing reconfigurable TMUXs, and examples are provided for illustration. [ABSTRACT FROM PUBLISHER]

This paper investigates the secure consensus tracking problem for continuous-time nonlinear multiagent systems with sensor attacks. By designing a secure data selector, the unattacked output data is extracted from a group of output measurements under sparse sensor attacks. Then, by virtue of the obtained data and neural networks, a state observer is constructed to estimate the unavailable system states, where the convex combination theory is introduced to reduce the difficulty of solving observation gains. To utilize the limited communication resources reasonably, a novel saturated threshold event-triggered control strategy is proposed to reduce control updates, and then each update is encoded into a binary signal (0 or 1) to further reduce the occupation of communication bandwidth. The designed control scheme ensures that all closed-loop signals are semi-globally uniformly ultimately bounded, and its effectiveness is verified via a simulation of attitude control of unmanned aerial vehicles. [ABSTRACT FROM AUTHOR]

An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed BER < 10^-14 at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10^-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V. [ABSTRACT FROM PUBLISHER]

This paper presents the analysis and design of a quadrature charge-domain down-conversion sampling mixer with embedded finite-impulse-response (FIR), infinite-impulse-response (IIR), and 4-path bandpass filters. An in-depth investigation of the principles of periodic impulse sampling, periodic windowed sampling, and periodic N-path windowed sampling is presented and their characteristics are compared. A detailed mathematical treatment of charge-domain windowed samplers with built-in sinc, FIR and IIR filters is provided. A quadrature charge-domain sampler with embedded FIR, IIR, and 4-path band-pass filters is proposed and its performance including the effect of the non-idealities of devices is investigated. The proposed design is implemented in an IBM 130 nm 1.2 V CMOS technology. Simulation results demonstrate that the proposed design is tunable over 50–250 MHz frequency range. For an 100 MHz input, the proposed design exhibits 70 dB aliasing rejection, 60 dB stop band attenuation while consuming current of 145 \muA. The performance of the proposed design is further validated using the results of on-wafer measurement of the fabricated microchip. [ABSTRACT FROM AUTHOR]

In this paper, we present a bang-bang phase detector (BBPD) and a delay-line frequency discriminator-based phase noise filter (PNF). With a larger phase detection gain, the BBPD-based PNF enhances the sensitivity by suppressing the charge pump noise. A time-amplifier and a five times voting machine are introduced together with the sense-amplifier-flip-flop to minimize the BBPD noise to make its effects negligible in the PNF sensitivity. At 1-MHz offset, the PNF demonstrates 15-dB phase noise suppression with −120.2-dBc/Hz sensitivity. Its phase noise suppression offset frequency is from 100 kHz to 8 MHz with 10–10.1-GHz input frequency range. The circuit is fabricated in a 65-nm CMOS technology, and dissipates 98-mW power. [ABSTRACT FROM PUBLISHER]

This paper presents the theoretical introduction and experimental validation of the “Class-J2 Mode Power Amplifier,” which provides higher efficiency and output power compared with conventional class-J mode counterpart. This mode of operation is realized by injection of the second-harmonic current to drain node of a class-J power amplifier (PA) to reduce the 45° phase shift between drain current and voltage signals. Similar to class-J PAs, the second-harmonic impedance of class-J2 PAs is purely reactive to simplify the design of the output matching network. The auxiliary second-harmonic injection circuit comprises a transistor biased in class-B mode followed by a class-C biased amplifier to achieve high second-harmonic current conversion efficiency. Theoretical formulations suggest that a 5% improvement in drain efficiency ( \eta D ) as well as a 1.5-dB increase in output power can be achieved for the class-J2 mode in comparison with the typical class-J operation. To check the accuracy of theoretical predictions, a proof-of-concept 1-GHz class-J2 PA with 12.2-dBm output power and 43% PAE is implemented in a 0.18- \mu \textm CMOS technology. For better comparison, a 1-GHz class-J PA with the same transistor size and bias condition as the class-J2 PA is also fabricated. The output power and PAE of the reference class-J PA are 11.4 dBm and 40.6%, respectively, which are in agreement with theoretical predictions. [ABSTRACT FROM PUBLISHER]

A low-power continuous-time delta-sigma modulator (CTDSM) incorporating a multi-bit feedback-assisted quantizer (FBAQ) is presented in this paper. The proposed multi-bit quantizer is placed in a negative feedback loop to reduce the signal swing at its input. As a result, the number of comparator required for signal quantization is reduced. Furthermore, the modulator is optimized for low-voltage swing operation, in which the excess-loop-delay compensation is embedded without requiring additional hardware. With a 240-MHz sampling clock, this CTDSM achieves a peak SNDR of 68.3 dB and a dynamic range of 71 dB over a 5-MHz signal bandwidth. Fabricated in a 90-nm CMOS process, this chip consumes 4.6 mW from a 1-V supply, which corresponds to a figure of merit (FoM) of 216 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

The generation of complex signal sources is important for test and validation of electronic systems. With reference to noise sources, commercial systems usually provide white noise sources, while the scientific literature only recently proposed circuits that generate programmable colored noise. This paper proposes a filtering circuit and an algorithm to design the same that produces an arbitrary colored electrical noise. The proposed system improves the performances of the previously proposed circuits in terms of spectral characteristics of the output, in terms of logic resource occupation and power dissipation, while providing no penalty on the working frequency. [ABSTRACT FROM AUTHOR]

Digital Storage Oscilloscopes (DSOs) conjugate high performance with large number of features and flexibility. The basic structure, based on fast Analog to Digital Converter (ADC) and memory, is augmented with several components for channel matching and bandwidth improvement, and processors that provide visualization, frequency processing, jitter and stability measurement, etc. Unfortunately, fine resolution in sample rate selection is not available, such that for several applications the user must run complex measurement procedures that require data download and offline processing. The paper proposes a dedicated digital circuit that offers fine control of the time-base by real time downsampling the input stream at an almost arbitrary sampling rate. The proposed circuit implements a series of operations involving real-time data filtering, defragmentation and packing, which are not considered by alternative approaches, like those based on polyphase filters, that offer very limited choices for the sampling rate. The circuit is designed to work in conjunction with the highest performance DSOs that use a multichannel architecture. Design rules for circuit design are provided together with implementation results in 14nm FinFET technology. When designed for an architecture with 64 channels with 8bit input samples the circuit works in real time with a sampling rate of 220 GSps running at 3.42 GHz, with a silicon footprint of 0.17 mm2 and a power dissipation of 0.85W. [ABSTRACT FROM AUTHOR]

This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard $0.18~\mu \text{m}$ CMOS process with an area of 0.57 mm2, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes $1.53~\mu \text{W}$ with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling. [ABSTRACT FROM AUTHOR]

The Ring-AllReduce framework is currently the most popular solution to deploy industry-level distributed machine learning tasks. However, only about half of the maximum bandwidth can be achieved in the optimal condition. In recent years, several in-network aggregation frameworks have been proposed to overcome the drawback, but limited hardware information have been disclosed. In this paper, we propose a scalable fully-pipelined architecture that handles tasks like forwarding, aggregation and retransmission with no bandwidth loss. The architecture is implemented on a Xilinx Ultrascale FPGA that connects to 8 working servers with 10 Gb/s network adapters, and it is able to scale to more complicated scenarios involving more workers. Compared with Ring-AllReduce, using AllReduce-Switch improves the efficient bandwidth of AllReduce communication with a ratio of $1.75\times $. In image training tasks, the proposed hardware architecture helps to achieve up to $1.67\times $ speedup to the training process. For computing-intensive models, the speedup from communication may be partially hidden by computing. In particular, for ResNet-50, AllReduce-Switch improves the training process with MPI and NCCL by $1.30\times $ and $1.04\times $ respectively. [ABSTRACT FROM AUTHOR]

This paper investigates an ultra-broadband sampling technique based on charge sampling using an Integrate-and-Hold Circuit (IHC) and ultra-short integration times. The charge sampling technique is mathematically analyzed in detail and compared to conventional switched-capacitor sampling. The mathematical analysis allows to predict the sampler bandwidth as well as the degradation of sampling precision due to analog circuit impairments such as integrator gain error, integration capacitor leakage, hold-mode droop, thermal noise, and clock jitter. Furthermore, design, simulation, and measurement results of an ultra-broadband charge sampler IC in SiGe BiCMOS technology are presented. The charge sampler IC achieves a 1dB bandwidth of 70 GHz. A resolution of better than 5.9 effective number of bits (ENOB) is measured from 0 to 70 GHz at a sampling rate of 5 GS/s. The results suggest that charge sampling using an IHC is a viable concept for ultra-broadband sampling. [ABSTRACT FROM AUTHOR]

This paper presents direct sequence spread spectrum (DS/SS) datalinks operating at 92-100 GHz with spreading factors up to 100K. Unlike traditional DS/SS datalinks which rely on preamble and cyclic dispreading for synchronization, the reported datalink uses a self-synchronous demodulation scheme, avoiding the large hardware complexity associated with exceptionally large spreading factors, and avoiding the difficulties of synchronizing the long de-spreading codes that are applicable to mm-wave systems. A demonstration link chipset is presented operating at 92-100 GHz with a spreading factor of 104K and a spread bandwidth of 6.0 GHz (baseband bandwidth of 56Kb/s) while consuming a total of 425mW. [ABSTRACT FROM AUTHOR]

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area. [ABSTRACT FROM AUTHOR]

This paper presents a feedback receiver for the digital predistortion (DPD) of radio frequency (RF) power amplifiers (PAs). In contrast to conventional architectures, the receiver samples in the frequency domain. By randomly selecting a frequency bin in each sampling interval, the PA model is identified with substantially lower acquisition bandwidth and sampling rate. The receiver prototype is implemented in a 28-nm FD-SOI technology and samples at 4MS/s instead of the full Nyquist rate of 168MS/s for a 20-MHz Long Term Evolution (LTE) signal with spectral regrowth. The prototype is shown to linearize a 4-W small base station power amplifier from an adjacent channel leakage ratio (ACLR) of −35 dBc to −47.7 dBc, after processing only about 250 samples. [ABSTRACT FROM AUTHOR]

In this paper, two output matching networks (OMNs) are proposed for integrated class-J and class-J−1 mode power amplifiers (PAs). The first MN provides the required load impedances of the class-J mode (i.e., $Z(f_{0})=R_{\mathrm{ opt}}+jR_{\mathrm{ opt}}$ and $Z({2}f_{0})=-j({3}\pi /{8})R_{\mathrm{ opt}}$), whereas the second MN realizes the optimal impedances of class-J−1 PAs (i.e., $Z(f_{0})=R_{\mathrm{ opt}}-jR_{\mathrm{ opt}}$ and $Z({2}f_{0})=j({3}\pi /{8})R_{\mathrm{ opt}}$). Detailed theoretical analyses are presented for each MN, and the values of matching components (i.e., inductors and capacitors) are obtained in terms of $R_{\mathrm{ opt}}$. Analytical derivations are verified by simulation results, while bandwidth and loss performances of each MN are also characterized. Two proof-of-concept class-J and class-J−1 PAs are designed and implemented in a 0.25- $\mu \text{m}$ GaAs process, where the proposed OMNs are employed in the designed circuits. The manufactured PAs show ≥28 dBm output power, ≥65% drain efficiency, and ≥61% power-added efficiency at 2 GHz. [ABSTRACT FROM AUTHOR]

Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CT ${\Delta \Sigma }$ Ms). Unfortunately, chopping causes the demodulation of shaped quantization noise into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, such as settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This paper gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given. [ABSTRACT FROM AUTHOR]