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This paper provides a comprehensive study of signal integrity issues in RRAM-based neuromorphic chip crossbar arrays due to interconnect parasitic. First, the parasitic parameters of the crossbar array are calculated by the partial equivalent element circuit (PEEC) method with an efficient unit-cell approach. Numerical experiments show that for a $50\times 50$ array scale, this method consumes only 1.5% of the calculation time of the commercial software based 3D model, which translates to a calculation speed up of 72 times. Moreover, the PEEC circuit simulation results match well with those of the 3D model. Then, we investigate the effects of parasitic parameters such as capacitance and inductance, as well as the feature size of the crossbar array on signal integrity. All of them will lead to corresponding changes in parasitic effects, which in turn result in the most common signal integrity issues such as crosstalk, time delay and mutual capacitive coupling induced sneak path problem. Different from other studies, the excitation used in this paper is the neural spike signal generated by the Izhikevich neuron model, which is both rich in dynamic characteristics and high in computational efficiency. Finally, based on the study we propose a simple but effective design scheme for reduction of signal distortion, which can provide valuable design guidance for neuromorphic systems to achieve high performance and high computational accuracy. [ABSTRACT FROM AUTHOR]

A well-performed capacitive power transfer (CPT) system highly depends on its compensation to achieve load-independent (LI) output and zero phase angle (ZPA) operation. It is particularly meaningful to maintain these objectives under various misalignments. This paper is devoted to a general and comprehensive method to study and explore all the potential high-order compensations. The coupler parameter variation is evaluated under different types of misalignment, and misalignment-insensitive (MI) parameters are properly designed for MI resonance. A general and straightforward decomposition and synthesis method is then proposed to generate the high-order resonant tanks. With the help of inverse ABCD parameters, all tank candidates are further judged by their capability for LI output and ZPA operation. Finally, two example CPT systems are built to verify the LI output and ZPA operation under misalignment. [ABSTRACT FROM AUTHOR]

Neural networks (NNs) with large scales of artificial neurons are increasingly used in recognition and classification tasks. In power-constrained scenarios, the tradeoff between performance and hardware consumptions must be carefully evaluated before silicon tape-out. In this paper, we proposed a systematic approach to design ultra-low power NN system. This work is motivated by the facts that NNs are resilient to approximation in many of the computations and NNs are outputting statistical tensors which are acceptable to less-than-perfect results. We resort to the front-back end approach with a twofold aim: (1) a fast and accurate design approach is proposed by estimating the computing quality of low-power approximate adder arrays, and it is adopted to evaluate the neural network system; (2) a quality configurable engine with different approximation degrees while processing NNs is implemented. The proposed work is demonstrated with a comprehensive keyword spotting (KWS) system as an ultra-low power NN engine. The experimental environment is setup with ten keywords from the google speech command dataset (GSCD) using an industrial 22-nm ultra-low-leakage (ULL) process. Comparing to the state-of-the-art KWS processors, the proposed approximate NN engine can demonstrate over 60% improvement in power efficiency and $1.1\times $ area efficiency while achieving similar recognition accuracy. [ABSTRACT FROM AUTHOR]

Instability and oscillation issues originating in high-voltage direct current (HVDC) systems comprising modular multilevel converters (MMCs) are gaining increasing interest in the research community. To detect such phenomena in advance, considerable effort has been devoted recently to developing MMC models for small-signal analysis. The derivation of such models is a challenging task due to the topology and complex control structure of MMCs, which results in them having a multi-frequency response. To address this issue, scholars developed methods based on dynamic phasors and harmonic state-space modelling, which, however, require extensive pen-and-paper computations. In this paper, the periodic small-signal analysis (PAC) is adopted to determine numerically several MMCs transfer functions. Such functions can be computed between any electrical circuit node or input/output port, without the need to recast the three-phase average MMC model to derive a linear equivalent one, possibly in the DQ-frame. We show how vector fitting allows converting these functions to equivalent algebraic representations, which can be profitably used to design MMCs and study their stability following some parameter changes. To showcase this feature, we exploit one of these transfer functions to detect DC-side instability in a point-to-point HVDC system. [ABSTRACT FROM AUTHOR]

In the context of global integration, the theory of financial complex networks has made significant contributions to the establishment of stable financial systems and effective regulatory systems. This survey paper presents a systematic methodology for the multi-layer financial complex networks and their applications. Several typical financial networks in existing research are first summarized: the interbank network, the credit network, the international trade network, and the dealer network. The main methods used in the existing literature to analyze the structure of financial networks include maximum entropy methods, network characterization, community detection, and dynamic multi-layer network. Financial risk contagion as well as spillover effects are the core issues that most of the literature focuses on. Finally, this paper reviews the shortcomings of the existing literature and suggests future research directions in this area. [ABSTRACT FROM AUTHOR]

Injection-locked ring oscillators (ILROs) are widely used for quadrature clock generators (QCG) in multi-lane wireline or optical transceivers because of their low power, low area, and technology scalability. However, locking a four-stage I/Q oscillator with a two-phase injection signal generates imbalances in amplitude and phase, resulting in I/Q phase errors and degraded jitter performance. This paper proposes a modified frequency-domain analysis with amplitude constraint for even-phase ILROs. Combining theoretical derivations with simulation results in 28nm CMOS technology, the behaviors of ring oscillators with partial injection and ILRO-based QCG are discussed and concluded. [ABSTRACT FROM AUTHOR]

This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transistor-level simulations. Next, the design of a 180-nm PFM chip with programmable weights is presented, and full image convolutions are demonstrated with the analog hardware. Preliminary chip measurements for a 45-nm implementation are also included to demonstrate process scalability. Design considerations for porting this architecture to nanometer processes, including FinFET technologies, are then discussed. This paper concludes with a simulation study on scaling down to 10 nm using a predictive technology model. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear analytical model for an inverter-based switched-capacitor Class-D RF power amplifier (SCDPA). The root causes of the SCDPA AMAM and AMPM nonlinearities are studied. The major factors affecting SCDPA nonlinearities are identified as the unequal on-resistances of selected cell and unselected cell. Specifically, time-varying resistance of the switch, different transistor responses during the transition and parasitic resistance on the supply path (IR drop) are analyzed. Then, the system-level result, like EVM and power spectral density, can be obtained with nonlinear behavior of PA. The results of model calculation, schematic simulation, and measurement are presented and compared with validate the model both on transistor level and system level. This paper, for the first time, provides an accurate design guidance to enable fast architecture study and quick circuit-level prototype with close-to-optimum component initial parameters. It can be expanded to more architectures, therefore helps to pave the path to future design automation for highly linear SCDPAs. [ABSTRACT FROM AUTHOR]

This paper studies the automation of the distortion analysis of multistage operational amplifiers by a symbolic analysis. The goal is to generate the readable closed-form design equations that relate the frequency-dependent harmonic distortion (HD) features, such as dc level, corner frequency, peaking, and zero, to the circuit parameters (including the nonlinearity coefficients). Prior research achieved such kind of characterization by carrying out the traditional signal-flow graph (SFG) analysis, which is highly algebra-involved and depends mainly on the manual derivation. This paper achieves automation by formulating a multiport circuit analysis strategy and applying a topological symbolic analysis method as an intermediate step in generating nodal transfer functions. The frequency-dependent HD factors are then characterized by analytically forming proper virtual current sources associated with the nonlinearity of each stage, modeled by a cubic polynomial. Implementation shows that the proposed tool can generate approximate closed-form HD characterization with comparable accuracy to full transistor-level simulation. The proposed automation tool can substantially mitigate heavy manual derivation work required by the existing SFG-based methods. Theory, software implementation, and circuit application are covered in detail. [ABSTRACT FROM AUTHOR]

Cartesian feedback (CF) linearization for radio amplifiers is appealingly simple, but it imposes a trade-off between signal bandwidth and feedback delay. In almost all of the CF literature, it is a first-order circuit. In this paper, we examine two second-order CF linearizers and show that they can provide deeper suppression of intermodulation distortion or greater signal bandwidth at a given loop delay. Twin-loop CF with damping factor 0.707, for example, can provide 20 dB lower intermodulation distortion and half the error vector magnitude (EVM), relative to first-order CF. For twin-loop CF and proportional-integrator CF, we provide the first analyses of their behavior, stability limits, and linearization performance. Comparison with simulations using nonlinear amplifier models shows both the value and the shortcomings of linear analysis. Our new spectral separation approach leads to insights about linearization and EVM. [ABSTRACT FROM AUTHOR]

This paper presents an energy-efficient spectral analysis method for the Internet of Things (IoT). The objective of this paper is to reduce the energy consumption of edge devices. The proposed method uses an autoregressive (AR) model for spectral analysis instead of the discrete Fourier transform, and its calculation process is distributed to the edge device and a base station by considering the energy consumption tradeoff of the data processing and the data communication. In this paper, the Yule–Walker method is employed for the AR coefficient calculation. The calculation process of Yule–Walker method can be divided into two parts: an autocorrelation calculation and an AR coefficient calculation. The autocorrelation calculation is implemented in the edge devices, and its dedicated hardware is designed using Verilog HDL. Meanwhile, the AR coefficient is calculated in the base station and is used for the spectral analysis. According to this distributed processing approach, the energy consumption of the edge device can be reduced compared with conventional DFT approaches using the fast Fourier transform (FFT). The system level energy consumption is evaluated assuming the IoT edge device, which has a wireless transceiver using Bluetooth low energy. The evaluation results show that the proposed method can reduce 79% of the edge device energy consumption for spectral analysis in a practical application. [ABSTRACT FROM AUTHOR]

An automatic inductor design process is helpful to reduce the design cycle of radio frequency (RF) integrated circuit (IC). This paper proposed an efficient synthesis-analysis machine (SAM) for on-chip inductor synthesis and modeling, as well as an automatic dataset generation (ADG) topology for the generation of artificial neural networks (ANNs) training dataset. The SAM consists of a synthesis ANN, two analysis ANNs and a proposed self-inspection machine (SIM). For a given design request, the SAM synthesizes a layout first, followed by analyzing the performance of the layout automatically, and finally improves the layout confidence through self-inspection. Compared to the modeling functions of analysis ANN, the synthesis ANN behaves as an inverse model, of which the inputs are desired inductor performances while the outputs are geometrical parameters of the layout. However, multi-value problems might occur in obtaining geometries of inductors, suggesting with evidence from mathematic relationships between geometrical and electrical parameters of an inductor. A multi-valued training dataset will mislead the synthesis ANN, resulting in unqualified layouts. To deal with this issue, a solution space contraction technique (SSCM) is also proposed. Furthermore, the SIM suspends most of the failures by comparing the output of analysis ANN back to the input of synthesis ANN. An electromagnetic simulation tool is used for experiments, and the effectiveness of the proposed SAM is proven by 6,500 inductor samples. [ABSTRACT FROM AUTHOR]

Recent studies on integrated circuits interconnections are mainly concentrated on the analysis of crosstalk and delay, by taking the trade-off between accuracy, speed, and complexity into consideration. The new idea of this paper is to apply the convex optimization method to analyze crosstalk and delay of the lossy coupled interconnections in identical and non-identical forms. For this purpose, a simple and comprehensive model is proposed to cover the functional and dynamic crosstalk in a computationally-effective way. More specifically, various case studies are determined to analyze the transient response of the coupled transmission lines with arbitrary excitation sources in the presence of both capacitive and inductive coupling characteristics. To validate the model, the numerical and Advanced Design System (ADS) simulation results are compared to indicate the desired accuracy. The calculated crosstalk percentage error of the proposed model with respect to ADS and HSPICE are less than 1.03% and 1.19%, respectively. In addition, the computational speed of the proposed method is about twice higher than ADS and HSPICE. The proposed model is extendible to handle ${N}$ coupled lines, making it appropriate to model complex integrated circuit interconnections. [ABSTRACT FROM AUTHOR]

Virtual platform frameworks have been extended to allow earlier soft error analysis of more realistic multicore systems (i.e., real software stacks and state-of-the-art ISAs). The high observability and simulation performance of underlying frameworks enable to generate and collect more error/failure-related data, considering complex software stack configurations, in a reasonable time. When dealing with sizeable failure-related data sets obtained from multiple fault campaigns, it is essential to filter out parameters (i.e., features) without a direct relationship with the system soft error analysis. In this regard, this paper proposes the use of supervised and unsupervised machine learning techniques, aiming to eliminate non-relevant information as well as identify the correlation between fault injection results and application and platform characteristics. This novel approach provides engineers with appropriate means to investigate new and more efficient fault mitigation techniques. The underlying approach is validated with an extensive data set gathered from more than 1.2 million fault injections, comprising several benchmarks, a Linux OS and parallelization libraries (e.g., MPI and OpenMP), as well as through a realistic automotive case study. [ABSTRACT FROM AUTHOR]

This paper analyzes the intermodulation between the element transition rate and the output-dependent unit switching distortion, i.e., the switching distortion of one switching unit, in current-steering digital-to-analog converters (DACs). The analysis and experimental results reveal how this intermodulation affects the DAC linearity. Based on this, we also propose a technique, termed random pairwise swapping (RPS) to improve the linearity of dynamic-element-matching-decoded DACs. Compared with existing techniques, RPS needs no half-cycle RZ operations and, thus, has no related vulnerabilities. In addition, the RPS could deal with the mismatch between different channels effectively. A 14-bit experimental DAC is fabricated in a 65-nm CMOS process. Measured results at 1.0-GS/s show above 72-dBc SFDR within 422-MHz bandwidth and 8–10-dB image tone suppression by the proposed RPS technique. At 3.0 GS/s, the SFDR is over 60 dBc within 600-MHz bandwidth. [ABSTRACT FROM AUTHOR]

Ten methods for finding through simulations the small-signal phase and gain margins of feedback circuits based on op-amps are described and analyzed in this mostly tutorial paper. The testbenches employed by these methods are presented and the corresponding analytical expressions of the return ratio are derived and compared against their “ideal” counterpart, obtained with standard circuit analysis; the requirement that the return ratio should not depend on the point it was measured at is also verified. These analyses are performed on a fairly general case: a generic reciprocal two-port network that closes a feedback loop around an op-amp acting as the forward amplifier. The four main types of op-amps were considered. The limitations of some of the tested methods are then highlighted by simulations. Besides the detailed analysis of previously reported methods, the paper proposes a novel method for deriving the return ratio of feedback circuits, that employs only current stimuli; it is demonstrated analytically that this method can be used for bilateral circuits, not only for op-amp-based (unilateral) ones. Also, a recent method for deriving directly the phase margin of a circuit is extended to estimating the gain margin, too. Conclusions on the accuracy and suitability of the analyzed methods for practical circuit cases are drawn. These results are then extended to other circuit topologies. [ABSTRACT FROM AUTHOR]

This paper presents models, circuit solutions and design procedures for maximized DC generation in inductively coupled RFID tags. An analytical model for the DC generation is derived, and relationships between the received signal in the tag coil antenna and the generated DC supply voltage using a voltage multiplier, based on both passive and active diodes, are presented. Derived from the trade-off between voltage gain in the multiplier and the tag coil at resonance, an equation for the optimum number of multiplier stages to achieve maximized DC generation is presented. Based on the derived equation, design examples are included with two typical tag coil antennas given a specification of the DC supply voltage and current. Also included in this paper is the design of a voltage multiplier based on active diodes implemented and manufactured in AMS 0.35 \mum CMOS process. The active diodes are based on a concept of threshold cancellation of MOS diodes and make use of reverse leakage control to achieve full threshold cancellation. [ABSTRACT FROM PUBLISHER]

Flexible electronics is rapidly evolving towards devices and circuits to enable numerous new applications. The high-performance, in terms of response speed, uniformity and reliability, remains a sticking point. The potential solutions for high-performance related challenges bring us back to the timetested silicon based electronics. However, the changes in the response of silicon based devices due to bending related stresses is a concern, especially because there are no suitable models to predict this behavior. This also makes the circuit design a difficult task. This paper reports advances in this direction, through our research on bendable piezoelectric oxide semiconductor field effect transistor (POSFET) based touch sensors. The analytical model of POSFET, complimented with Verilog- A model, is presented to describe the device behavior under normal force in planar and stressed conditions. Further, dynamic readout circuit compensation of POSFET devices have been analyzed and compared with similar arrangement to reduce the piezoresistive effect under tensile and compressive stresses. This approach introduces a first step towards the systematic modeling of stress induced changes in device response. This systematic study will help realize high-performance bendable microsystems with integrated sensors and readout circuitry on ultra-thin chips (UTCs) needed in various applications, in particular, the electronic skin (e-skin). [ABSTRACT FROM PUBLISHER]

The Direct RF-to-Digital $\Delta\Sigma$ receiver has emerged as an attractive solution for multi-band multi-standard wireless applications. This architecture is a direct RF to baseband digitizer with RF feedback from baseband to RF stages. The presence of the RF blocks such as the low noise amplifier and down-conversion mixer inside the loop filter significantly relaxes their linearity requirements and also improves the noise transfer function of the loop filter. However, the RF feedback poses several challenges, especially making the design methodology more complex. In contrast to classical receiver architectures, the blocks of the Direct RF-to-Digital $\Delta\Sigma$ receiver cannot be designed, analyzed, and simulated independently. Besides, conventional design methodologies for $\Delta\Sigma$ Modulators cannot be applied for this kind of receiver due to the presence of the RF blocks and the RF feedback inside the loop. This paper presents a new design methodology suited for this family of receivers. The proposed methodology covers simulation approaches, system design, and non-ideality impacts on the receiver. A design example of a multi-band multi-standard receiver for GSM/WCDMA/LTE is considered throughout the paper to demonstrate this design methodology. [ABSTRACT FROM PUBLISHER]

Many energy harvesters (EH) deliver an ac voltage and require a rectifier as a consequence. This paper describes how the rectifier affects the power flow transmitted from the EH to the load and how to tackle the different voltage amplitudes. This study has been performed using analytical calculations, numerical modeling and experiments. To reach the maximum power transfer, conventional methods apply a fraction of the open-circuit voltage delivered by the EH. In contrast, this study points out that the optimum operating point must be shifted by a quantity depending on the rectifier characteristics. This difference is particularly important when the EH provides relatively small ac voltages. Two classic rectifiers are covered: a diode bridge (DB) and a MOSFET bridge (MB). An approximated solution of the analytical model is proposed and allows to optimize the EH without cumbersome numerical computations. Experiments are conducted first with a function generator and then with an electromagnetic EH prototype. The outcomes from the analytical model and the numerical model are in good agreement with the experimental results. A new regulation method is proposed for maximizing the power transferred from the ac EH to the load. [ABSTRACT FROM AUTHOR]

Resampling technology is becoming increasingly critical, as different frequency components are required to be measured in one device. In this paper, a resampling method based on filter designed by window function is proposed to satisfy the requirements of different sampling rates. The frequency responses of the filter in the resampling model based on the Farrow structure are investigated, and the design criterion of the filter in the resampling model is proposed. A fractional delay filter design model based on window function method is established. A fractional delay filter coefficient matrix, which is expressed by a polynomial form, is constructed. Then, the expression related to the subfilter coefficients is obtained and subfilter coefficients are solved by the least-square method. The simulation results show that the filter designed by the proposed method has better performance when used for resampling as compared those designed by existing methods, and can efficiently prevent the occurrence of frequency aliasing and mirroring components in the process of sampling rate conversion. Therefore, the proposed method meets the conditions for application to existing measurement devices. [ABSTRACT FROM AUTHOR]

This paper addresses model-set-based quantitative analysis of feedback systems. In particular, we find a model set describing the subsystems such that the performance improvement of the feedback system is achieved. To this end, we introduce the parameter-integrated passivity to accurately describe each passive subsystem and their feedback system. A model set describing passive systems is characterized by the two matrix parameters. The matrix parameters enable to evaluate the $L_2$ -gain “of the model set”, which is defined as the $L_2$ -gain of the worst-case system in the model set. With the parameter-integrated passivity, the quantitative analysis of a feedback system composed of two passive subsystems is provided as the parameter transition. Then, we find conditions on the matrix parameters to achieve the performance improvement such that the $L_2$ -gain of the model set describing the feedback system is strictly less than that describing the subsystems. Subsequently, the performance improvement of the feedback system is extended to that of an iterative feedback system, which is a network system constructed by the feedback connection of multiple subsystems in a step-by-step manner. Then, we find conditions on the passivity parameters describing the baseline subsystem to achieve a gradual performance improvement with the subsystem connection. [ABSTRACT FROM AUTHOR]

This paper presents a novel time-variant model of multiplying delay-locked loops. A simple feed-forward model of the multiplexed ring oscillator mathematically describes the edge realignment process and, by providing an explicit tuning input, allows to be embedded into the time-variant multiplying delay-locked loop model without requiring approximations. Verification of the multiplexed ring oscillator model against detailed circuit simulations is presented. Closed-form expressions for the multiplying delay-locked loop phase noise, as a function of the system parameters and noise sources, are provided. [ABSTRACT FROM AUTHOR]

With the prevalence of COVID-19, the modeling of epidemic propagation and its analyses have played a significant role in controlling epidemics. However, individual behaviors, in particular the self-protection and migration, which have a strong influence on epidemic propagation, were always neglected in previous studies. In this paper, we mainly propose two models from the individual and population perspectives. In the first individual model, we introduce the individual protection degree that effectively suppresses the epidemic level as a stochastic variable to the SIRS model. In the alternative population model, an open Markov queueing network is constructed to investigate the individual number of each epidemic state, and we present an evolving population network via the migration of people. Besides, stochastic methods are applied to analyze both models. In various simulations, the infected probability, the number of individuals in each state and its limited distribution are demonstrated. [ABSTRACT FROM AUTHOR]

This paper reports on the dynamic behavior of dual coupled memristors (MRs) in serial and parallel connections in consideration of polarity combination and coupling strength. Based on the constitutive relations, two flux coupled MRs are adopted for demonstration to theoretically exhibit the variation of memductance in terms of flux, charge, voltage, and current. The coupled MRs are also serially connected with a regular resistor to further explore its memristive behavior. Theoretical analysis reported in this paper is confirmed via a simulation study, and then an experimental investigation is carried out using a practical circuit emulating the dual coupled MRs. Good agreement between experimental and simulation results confirms that dual coupled MRs in composite connections behave as a new MR with higher complexity. [ABSTRACT FROM AUTHOR]

This paper introduces a methodology able to produce an exact valid and physically meaningful circuit representation out of generic multi-port passive linear state-space models. The proposed method has a strong theoretical relevance as it allows the generation of equivalent netlists whose RLC values are guaranteed positive, without applying any additional approximations, and based only on coordinate transformations and circuit laws interpretation. In this sense it can be viewed as a generalization of Foster's synthesis that is guaranteed to produce a circuit description containing only elements with physical meaning. In addition, it also presents pratical advantages, as it generates a very sparse circuit, whose usage is highly efficient within standard simulation and analysis platforms. Furthermore, the synthesized circuit can be easily included in any standard environment for simulation, verification, delay calculation, symbolic analysis, etc., and in combination with other models for system-level detailed simulation, which further increases the practical relevance of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model for power harvester circuits used in Ultra-low power applications. Assuming that the MOS devices of the circuit fully operate in the Sub-threshold regime in both forward and reverse regions, closed-form equations for important properties of the rectifier circuit such as output voltage, efficiency and input resistance are derived. The model includes the effect of the compensation voltage on the circuit behavior. There is a good agreement between the simulation results and the model. In addition, the contour plots needed to simultaneously optimize the matching network and the rectifier circuit are derived by the resulting equations. A 50-Stage rectifier was fabricated in a 180-nm standard CMOS Process. The proposed model is verified with the measurement results. The model has a maximum error of 10% in comparison with the circuit simulation, and a maximum error of 12% with the measured values. [ABSTRACT FROM PUBLISHER]

Conventional analog-to-information converter (AIC) frameworks employ a discrete-time synthesis sparse model to deal with analog signals, which, however, induces a challenging basis mismatch problem. In this paper, we propose a novel AIC framework, called generalized AIC (G-AIC), to tackle this issue. In the new method, an analysis sparse model is taken, for the first time, as the prior information of analog signals being sampled at sub-Nyquist rate. Through the joint optimization for the discretization operator and its analysis sparse operator, the G-AIC removes the model error between an analog signal and its equivalent discrete samples. To validate the G-AIC framework, we design a single channel G-AIC system based on switched-capacitor (SC) circuits. The circuit design is presented at the theoretical-level, the system-level, and the transistor-level. Numerical simulations demonstrate the G-AIC system can well restore an analog signal from its sub-Nyquist measurements, even though its sparse basis is unknown. Compared with two state-of-the-art AIC systems, the new design can achieve at least 2dB reconstruction gain. In brief, the proposed method provides a promising alternative to exploit analog signals in sub-Nyquist sampling systems. [ABSTRACT FROM AUTHOR]

Pinched hysteresis behavior is considered evidence of the existence of the memristive element. Recently, the multi-lobes (more than two) behavior has been discovered in some memristive devices. In this paper, a fractional-order flux/voltage-controlled memristive model is introduced that is able to develop multiple symmetric and asymmetric pinch-off points. Generalized closed-form expressions for the necessary conditions of multiple pinch-off points existence are derived in addition to the coordinates of the pinch-off points in the $I\!-\!V$ plane. Closed-form expressions for the minimum and maximum achievable resistances are derived. Moreover, different illustrative numerical examples have been given verifying the calculated expressions. Finally, in order to verify the multiple pinch-off behaviors, the proposed emulator circuit is introduced, analyzed, and verified using both SPICE simulations and experiments to validate the proposed models. Different fractional-order cases have been experimentally tested using different excitation signals such as sinusoidal, square, and triangular signals showing the circuit-ability to generate the multiple pinch-off points. [ABSTRACT FROM AUTHOR]

Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CT ${\Delta \Sigma }$ Ms). Unfortunately, chopping causes the demodulation of shaped quantization noise into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, such as settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This paper gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given. [ABSTRACT FROM AUTHOR]

This paper deals with the $H_{\infty }$ fault detection (FD) problem for a class of buck converter with the transmission-induced multiplicative noises and the event-triggered scheme under the network environment. The model of buck converter is approximated by a nonlinear model, and it is further analyzed based on the electricity knowledge. Due to the dynamic characteristics of network transmission, multiplicative noises need to be considered, which are described as a product of some uncorrelated standardized normal distribution and the transmitted signal. Meanwhile, an event-triggered mechanism is utilized for the purpose of reducing the energy consumption, and an FD observer is designed to detect the fault presented in buck converter. Some novel sufficient conditions are given in terms of linear matrix inequalities to guarantee the robust stability of the FD system, and the $H_{\infty }$ optimal fault tracking performance index is also achieved. Finally, an illustrative example is provided to show the validity and merit of the proposed method. [ABSTRACT FROM AUTHOR]

This paper deals with the global dynamical analysis of an H-bridge parallel resonant converter under a zero current switching control. Due to the discontinuity of the vector field in this system, sliding dynamics may take place. Here, the sliding set is found to be an escaping region. Different tools are combined for studying the stability of oscillations of the system. The desired crossing limit cycles are computed by solving their initial value problem and their stability analysis is performed using Floquet theory. The resulting monodromy matrix reveals that these cycles are created according to a smooth cyclic-fold bifurcation. Under parameter variation, an unstable symmetric crossing limit cycle undergoes a crossing-sliding bifurcation leading to the creation of a symmetric unstable sliding limit cycle. Finally, this limit cycle undergoes a double homoclinic connection giving rise to two different unstable asymmetric sliding limit cycles. The analysis is performed using a piecewise-smooth dynamical model of a Filippov type. Sliding limit cycles divide the state plane in three basins of attraction, and hence, different steady-state solutions may coexist which may lead the system to start-up problems. Numerical simulations corroborate the theoretical predictions, which have been experimentally validated. [ABSTRACT FROM AUTHOR]

In this paper, we present a framework for analytically estimating the output quality of common digital signal processing (DSP) blocks that utilize approximate adders. The framework is based on considering the error of approximate adders as an additive noise (approximation noise) that disturbs the output of the DSP block in question. A signal processing theoretical modeling approach for describing the power of the approximation noise which is the integral of error spectral density over the bandwidth, is developed. The output qualities of DSP blocks, such as finite impulse response filter, discrete cosine transform, and fast Fourier transform, which utilize approximate adders, are thus estimated. The accuracy of the proposed framework is evaluated by comparing mathematical model predictions to simulation results by using the signal-to-noise ratio (SNR) metric. The inaccuracy of the SNRs predicted by the framework was, on average, less than 2.5dB compared with that obtained from simulations. Therefore, a mathematical optimization approach based on Lagrange Multipliers for optimizing design parameters is also presented. The optimization is realized by choosing a proper configuration of the target block, such as determining the data width of the inexact computation part for each approximate adder in the design. [ABSTRACT FROM AUTHOR]

Chopping is a technique to reduce offset and flicker noise in amplifiers by up-converting them to higher frequency, and subsequently filtering them out. A typical chopping implementation uses two complementary phases which have a finite non-overlap time in between them. When such a chopping phase is used in the first integrator of a continuous-time delta sigma modulator, the non-overlap time can significantly degrade two key parameters of the modulator’s performance—in-band noise and its inherent anti-aliasing. In this paper, we develop a model to include the effects of non-overlap duration on the modulator’s performance. Then this model is used to derive analytical expressions for in-band noise and anti-aliasing for a given non-overlap duration. The results obtained are verified using simulation. [ABSTRACT FROM AUTHOR]

Superconducting digital electronics, especially Single Flux Quantum (SFQ), has emerged as a promising beyond-CMOS technology with Josephson junctions (JJ) as the active device. It has the potential to meet the booming demands of lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Despite these promises, scaling SFQ circuits remains a serious challenge that motivates the support of multiple SFQ clock domains. Towards this end, this paper analyzes the impact of setup time violations and metastability in SFQ circuits comparing the derived analytical models to their CMOS counterparts. It also proposes new techniques to reduce the average latency in metastability-tolerant SFQ synchronizers, and evaluates their effects on the layout and critical margin of the design. It further extends the proposed model to estimate the Mean Time Between Failure (MTBF) of flip-flop-based synchronizers and shows that their MTBF with the current feature sizes is unaffected by noise, similar to CMOS. Finally, it curve fits this model to simulations using the state-of-the-art SFQ5ee process and shows that a two-flop SFQ synchronizer with a clock frequency of 25 GHz has an estimated MTBF of ~106 years. [ABSTRACT FROM AUTHOR]

Under process, voltage, and temperature variations, SRAM cell stability largely fluctuates from the nominal value. In the design step, SRAM cell optimization while ignoring the fluctuation induces the yield loss for the stability. Variation-aware optimization of an SRAM cell can prevent the yield loss problem by considering the mean and variance of SRAM cell stability when finding optimal design parameters. This paper proposes a novel SRAM optimization method that uses a deep neural network (DNN). Multiple DNNs from ensemble techniques represent the mean and variance of SRAM cell stability for the nominal design parameters. Subsequent sensitivity analysis of DNN extracts the ${K}$ design parameters that have the most dominant effects on the mean and variance of SRAM cell stability. Then multidimensional optimization is used to find the optimal values of these ${K}$ parameters to maximize the mean stability while minimizing its variance. The proposed method achieved an average of 2% error compared to MC simulation. The proposed optimization method takes only 561 s to provide the most optimal design parameter values of an SRAM cell. [ABSTRACT FROM AUTHOR]

An admittance or impedance matrix of a power converter is highly desirable for harmonic analysis of a power system. However, power converters are inherently nonlinear and time-varying systems. Therefore, a small-signal harmonic model needs to be derived. While there have been many methods to obtain the small-signal models of DC-DC converters, most of these methods cannot be directly applied to AC-DC converters. Moreover, while accurate methods exist for obtaining accurate models of open-loop AC-DC converters, there are few existing methods for obtaining accurate models for closed-loop AC-DC converters. This paper proposes an analytical method for obtaining an accurate small-signal harmonic model for a power converter. The proposed method is based on state-variable sensitivity methods, which have been previously used to derive a transfer function of a DC-DC converter. This paper will show what modifications are required to extend it to derive the small-signal harmonic model of a closed-loop AC-DC converter. A small-signal harmonic model of a closed-loop pulse-width modulated (PWM) voltage source converter (VSC) with synchronous frame current controllers and a dc voltage controller is derived based on the proposed method. The results are in good agreement with large-signal simulations by means of PSCAD/EMTDC. [ABSTRACT FROM AUTHOR]

Previous studies have shown that impulsive noise can weaken the performance of power line communication (PLC). Though DCSK can improve the performance in an order of magnitude comparing to the direct sequence differential phase shift keying (DS-DPSK), it is still a challenge to further improve the BER performance with signal redesign without the need of advanced and expensive extra noise suppression technologies. The paper introduces the model of asynchronous impulsive noise of Middleton class-A noise and corresponding multipath fading channels in PLC, and analyzes the bit error rate (BER) performance of the $M$ -ary differential chaos shift keying (MDCSK) scheme over different channels. Furthermore, a new replica piecewise frame of MDCSK (RP-MDCSK) is proposed to resist the impulse noise. In the proposed scheme, one piecewise of signals is transmitted first. Then, it replicates $pw$ times, which serves as the reference signal transmitted in the first half symbol period. The information-bearing signal combines the reference signal with its Hilbert transform in the second half. At the receiver, one piece of reference signals is extracted and then correlated with its corresponding information-bearing part. The BER expressions of the MDCSK and the proposed scheme are derived and analyzed over different channels, and verified by simulations. Comparing with the corresponding schemes, it is found that the BER of the proposed scheme is by 2–3 orders of magnitude lower. [ABSTRACT FROM AUTHOR]

In this paper, a new phase error analysis is introduced for rotary traveling wave oscillators (RTWOs). Two new analytical approaches are used to extract closed-form equations for the RTWOs phase error arising from asymmetric resonator and inequality of negative transconductors. Derived equations show that the phase error can be cancelled and even controlled by adjusting the bias current of negative transconductors without any undesirable changing in oscillation frequency. This characteristic is then used for introducing a new phase error calibration method for RTWOs. This calibration method is not limited by the problems that limit the usage of the prior calibration technique. Our theoretical results are compared with accurate simulations to evaluate the validity of the proposed analysis and accuracy of the closed-form equations. Simulations have been done in 0. 18- $\mu$ m CMOS technology with a 1.8-V supply voltage. The evaluations show good agreement between analytical phase-error equations and simulation results. Also, appropriate simulations confirm the validity of the calibration method that is introduced in this paper. [ABSTRACT FROM AUTHOR]

Analog integrated circuit designers always use closed-form design equations in design reasoning. However, most of the time, they have to derive all equations by hand. When high-order effects are of interest, manual derivation would become much harder. Although the art of symbolic circuit analysis has been making steady progress, symbolically generating closed-form equations for high-order effect is still a less well-studied subject. This paper proposes a novel symbolic computation method for generating the second-order characterization of differential cells. It is a perturbation approach that takes the advantage of structural symmetry in differential cells, and is formulated as a systematic computation procedure comprised of several intermediate steps, the computation of each step gives a compact partial expression. Examples are provided to illustrate that closed-form common-mode rejection ratio equations in pole-zero form (unknown before) for two classical operational amplifiers can be generated by applying the symbolic perturbation procedure. [ABSTRACT FROM AUTHOR]

Analyzing data with latent spatial and/or temporal structure is a challenge for machine learning. In this paper, we propose a novel nonlinear model for studying data with latent dependence structure. It successfully combines the concepts of Markov random fields, transductive learning, and regression, making heavy use of the notion of joint feature maps. Our transductive conditional random field regression model is able to infer the latent states by combining limited labeled data of high precision with unlabeled data containing measurement uncertainty. In this manner, we can propagate accurate information and greatly reduce uncertainty. We demonstrate the usefulness of our novel framework on generated time series data with the known temporal structure and successfully validate it on synthetic as well as real-world offshore data with the spatial structure from the oil industry to predict rock porosities from acoustic impedance data. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the 1-periodic schedule of a class of time interval models under the form of a polyhedron which can describe Timed Event Graphs and P-time Event Graphs. Using the duality and Stiemke's theorem, the main contribution is the determination of conditions where the extremum cycle times are finite and characteristic of a class of models. [ABSTRACT FROM AUTHOR]

This paper studies the problem of exactly identifying the structure of a probabilistic Boolean network (PBN) from a given set of samples, where PBNs are probabilistic extensions of Boolean networks. Cheng et al. studied the problem while focusing on PBNs consisting of pairs of AND/OR functions. This paper considers PBNs consisting of Boolean threshold functions while focusing on those threshold functions that have unit coefficients. The treatment of Boolean threshold functions, and triplets and n -tuplets of such functions, necessitates a deepening of the theoretical analyses. It is shown that wide classes of PBNs with such threshold functions can be exactly identified from samples under reasonable constraints, which include: 1) PBNs in which any number of threshold functions can be assigned provided that all have the same number of input variables and 2) PBNs consisting of pairs of threshold functions with different numbers of input variables. It is also shown that the problem of deciding the equivalence of two Boolean threshold functions is solvable in pseudopolynomial time but remains co-NP complete. [ABSTRACT FROM AUTHOR]

This paper presents a system, where clocked comparators consuming only CV^2 energy directly derive classification decisions from analog sensor signals, thereby replacing instrumentation amplifiers, ADCs, and digital MACs, as typically required. A machine-learning algorithm for training the classifier is presented, which enables circuit non-idealities as well as severe energy/area scaling in analog circuits to be overcome. Furthermore, a noise model of the system is presented and experimentally verified, providing a means to predict and optimize classification error probability in a given application. The noise model shows that superior noise efficiency is achieved by the comparator-based system compared with a system based on linear low-noise amplifiers. A prototype in 130-nm CMOS performs image recognition of handwritten numerical digits, by taking raw analog pixels as the inputs. Due to pin limitations on the chip, the images with $28\times 28=784$ pixels are resized and downsampled to give 47 pixel features, yielding an accuracy of 90% for an ideal ten-way classification system (MATLAB simulated). The prototype comparator-based system achieves equivalent performance with a total energy of 543 pJ per ten-way classification at a rate up to 1.3 M images per second, representing $33\times $ lower energy than an ADC/digital-MAC system. [ABSTRACT FROM AUTHOR]

We consider an environmentwhere players need to decide whether to buy a certain product (or adopt a technology) or not. The product is either good or bad, but its true value is unknown to the players. Instead, each player has her own private information on its quality. Each player can observe the previous actions of other players and estimate the quality of the product. A classic result in the literature shows that in similar settings, informational cascades occur, where learning stops for the whole network and players repeat the actions of their predecessors. In contrast to this literature, in this paper, players get more than one opportunity to act. In each turn, a player is chosen uniformly at random from all the players and can decide to buy the product and leave the market or wait. Her utility is the total expected discounted reward, and thus, myopic strategies may not constitute equilibria. We provide a characterization of perfect Bayesian equilibria (PBEs) with forward-looking strategies through a fixed-point equation of dimensionality that grows only quadratically with the number of players. Using this tractable fixed-point equation, we show the existence of a PBE and characterize PBEs with threshold strategies. Based on this characterization, we study informational cascades in two regimes. First, we show that for a discount factor $\delta$ strictly smaller than 1, informational cascades happen with high probability as the number of players $N$ increases. Furthermore, only a small portion of the total information in the system is revealed before a cascade occurs. Second, and more surprisingly, we show that for a fixed $N$ , and for a sufficiently large $\delta < 1$ , when the product is bad, there exists an equilibrium where an informational cascade can happen only after at least half of the players revealed their private information, and consequently, the probability for a “bad cascade” where all the players buy the product vanishes exponentially with $N$. Finally, when $\delta =1$ and the product is bad, there exists an equilibrium where informational cascades do not happen at all. [ABSTRACT FROM AUTHOR]

Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian proposed an idealized trap model with the goal of capturing the nonstationary behavior of oxide traps, and were able to elucidate the experimentally observed large noise power reduction in switched MOSFET circuits which eluded any explanation obtainable with legacy stationary models. In this paper, we build on their seminal work and first identify an oversight in their model derivation which had produced an incorrect expression for the single trap noise spectrum. We next derive the correct spectrum expression, verify it against detailed idealized trap simulations and discuss its implications. The idealized trap model is amenable to analytical derivations and useful as a first stage in understanding nonstationary trap noise. We then demonstrate that noise simulations based on a detailed trap description implemented in a compact MOSFET model in a circuit simulator are needed for an accurate characterization of low-frequency noise in switched MOSFET circuits that matches experimental results. [ABSTRACT FROM AUTHOR]

Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to those of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology. [ABSTRACT FROM AUTHOR]

One of the main causes of expensive IC redesigns is a failure to meet electromagnetic compatibility (EMC) requirements. For this reason, there is a huge demand for verification methods to identify and prevent immunity failures on chip. Strongly nonlinear effects, in particular DC operating point shifts, are a major cause of such immunity failures. Conventional analysis techniques, used to simulate these strongly nonlinear effects, suffer from a few drawbacks. They can be time-consuming and suffer from convergence issues. Moreover, they do not provide insight into the root causes of the nonlinear behavior. In this paper, an automated method is proposed that overcomes the mentioned drawbacks and identifies causes of immunity failures by listing critical distortion contributions. The method is applicable to very large, strongly nonlinear integrated circuits. It uses a simple model that determines the nonlinear contribution of one device in its linearized environment. Because the computation time is negligible, the analysis can be repeated for many devices and interference frequencies. Additionally, the method gives insight into the drivers responsible for the distortion effects, such that the designer can efficiently solve the problem. The method is demonstrated by applying it to a practical test case. [ABSTRACT FROM AUTHOR]

In recent times, sequence-to-sequence (seq2seq) models have gained a lot of popularity and provide state-of-the-art performance in a wide variety of tasks, such as machine translation, headline generation, text summarization, speech-to-text conversion, and image caption generation. The underlying framework for all these models is usually a deep neural network comprising an encoder and a decoder. Although simple encoder–decoder models produce competitive results, many researchers have proposed additional improvements over these seq2seq models, e.g., using an attention-based model over the input, pointer-generation models, and self-attention models. However, such seq2seq models suffer from two common problems: 1) exposure bias and 2) inconsistency between train/test measurement. Recently, a completely novel point of view has emerged in addressing these two problems in seq2seq models, leveraging methods from reinforcement learning (RL). In this survey, we consider seq2seq problems from the RL point of view and provide a formulation combining the power of RL methods in decision-making with seq2seq models that enable remembering long-term memories. We present some of the most recent frameworks that combine the concepts from RL and deep neural networks. Our work aims to provide insights into some of the problems that inherently arise with current approaches and how we can address them with better RL models. We also provide the source code for implementing most of the RL models discussed in this paper to support the complex task of abstractive text summarization and provide some targeted experiments for these RL models, both in terms of performance and training time. [ABSTRACT FROM AUTHOR]

The best linear approximation (BLA) framework has already proven to be a valuable tool to analyze nonlinear systems and to start the nonlinear modeling process. The existing BLA framework is limited to systems with additive (colored) noise at the output. Such a noise framework is a simplified representation of reality. Process noise can play an important role in many real-life applications.This paper generalizes the best linear approximation framework to account also for the process noise, both for the open-loop and the closed-loop setting, and shows that the most important properties of the existing BLA framework remain valid. The impact of the process noise contributions on the robust BLA estimation method is also analyzed. [ABSTRACT FROM AUTHOR]