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This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

This paper presents research and implementation of a high frequency Integer-N phase-locked loop for digital beamforming in mobile devices. Multiple topologies investigated whereof two were implemented. The transient phase noise of the PLL is -104dB/-95dB @1MHz. The output frequency range is from 8G-10G. Reference signal is 163.84MHz, reference-spurs is -80dBc/-98dBc lower than main frequency. RMS jitter is about 38fs/68fs. Locking time is less than 3.5us. The implementation consists of an LC-tank VCO with extra tail filtering. Divider chain consisting of a dual module prescaler/CML prescaler followed by a programmable divider. Charge pump with compensation method and a cascoded gain-boosting charge pump is used to decrease current mismatch. Tri-state phase detector and lastly a third-order passive loop filter. Supply voltage at 0.8V is used in the design. Total power consumption is less than 10mW. The PLL system was implemented in the CMOS FD-SOI 22nm process and simulations executed in the Virtuoso Cadence environment. Limitations and possible improvements are listed in the end., The upcoming 5G-New Radio Standard will enable cellular communication in the millimeter-Wave (mmWave) frequency bands,24-100GHz. These frequency bands will open up for large system bandwidth and tremendously high data rates enabling lots of new use cases, such as smart cities, connected cars, medical applications and much more! Given this cutting-edge technology, exciting challenges arises for today's RF designers that requires state-of-the-art solutions. High isotropic path loss between radio transmitters and radio receivers makes it necessary to rely on antenna arrays with large number of antenna elements. MIMO stands for Multiple-Input-Multiple-Output. In reality this means using multiple antennas on the same frequency band, with massive indicating a high number of such antennas. Making these antennas directional through beamforming, focusing the transmission in the direction of the receiving party, may overcome the issues with isotropic path loss. Traditionally mmWave has been used more for short-range communication due to its inherent characteristics and propagation loss, but in combination with MIMO and beamforming it will take the next generations of cellular communication to new levels! Small antennas needed for mmWave open possibilities to integrate the RFIC, front end radio modules, filters, and antenna element in a singe RF chip. This fact, in combination with that 5G-NR is standardized for communication also over mmWave radio frequencies which enables mmWave communication in smartphone and IoT devices, will drastically change the way beamforming will be implemented in mobile devices in the future! A critical component used in wireless communications that will be included in this type of integrated chip is the, so called, phase-locked loop (PLL). The PLL is a feedback system which can generate a periodic precise signal at a certain frequency and phase. This ability is quite useful and can be applied in various applications for frequency synthesis. Facing

[ES] En este trabajo se presenta un sistema de lectura RFID para la detección y determinación de la dirección de movimiento de etiquetas de identificación por radiofrecuencia (RFID) instaladas en vehículos. Este sistema se centra en la adaptación de tecnología de radares secundarios, específicamente, la aplicación de técnicas monopulso utilizados en SSR (Radar Secundario de Vigilancia), a la antena de lectura. La antena monopulso se integra en los lectores RFID pasivos que funcionan en la banda ISM de 915 MHz (Industrial, Scientific and Medical) para aplicaciones de Sistemas Inteligentes de Transporte (ITS). El sistema proporciona la dirección de movimiento de un objeto que cuenta con una etiqueta RFID instalada, así como la lectura del código único de la etiqueta, por medio de una única antena monopulso e interrogador RFID y un sistema de detección de fase que filtra las señales recibidas por la antena e identifica el cambio de polaridad en el voltaje de la señal lo que permite determinar el sentido de movimiento de la etiqueta. El sistema se propone para aplicaciones de Sistemas Inteligentes de Transporte (ITS), de igual manera puede ser de utilidad en procesos de control de inventarios, logística, sistemas de seguridad y control de acceso., [EN] This paper presents an RFID reading system for detecting and determining the direction of movement of radio frequency identification (RFID) tags installed in vehicles. This system focuses on the adaptation of secondary radar technology, specifically, the application of monopulse techniques used in SSR (Secondary Surveillance Radar), to the reading antenna. The monopulse antenna is integrated into passive RFID readers that operate in the 915 MHz ISM band (Industrial, Scientific and Medical) for Intelligent Transport Systems (ITS) applications. The system provides the direction of movement of an object that has an RFID tag installed, as well as the reading of the unique code of the tag, by means of a single monopulse antenna and RFID interrogator and a phase detection system that filters the signals received by the antenna and identifies the polarity change in the signal voltage which allows determining the direction of movement of the tag. The system is proposed for applications of Intelligent Transport Systems (ITS), similarly it can be useful in processes of inventory control, logistics, security systems and access control

[ES] En este trabajo se presenta un sistema de lectura RFID para la detección y determinación de la dirección de movimiento de etiquetas de identificación por radiofrecuencia (RFID) instaladas en vehículos. Este sistema se centra en la adaptación de tecnología de radares secundarios, específicamente, la aplicación de técnicas monopulso utilizados en SSR (Radar Secundario de Vigilancia), a la antena de lectura. La antena monopulso se integra en los lectores RFID pasivos que funcionan en la banda ISM de 915 MHz (Industrial, Scientific and Medical) para aplicaciones de Sistemas Inteligentes de Transporte (ITS). El sistema proporciona la dirección de movimiento de un objeto que cuenta con una etiqueta RFID instalada, así como la lectura del código único de la etiqueta, por medio de una única antena monopulso e interrogador RFID y un sistema de detección de fase que filtra las señales recibidas por la antena e identifica el cambio de polaridad en el voltaje de la señal lo que permite determinar el sentido de movimiento de la etiqueta. El sistema se propone para aplicaciones de Sistemas Inteligentes de Transporte (ITS), de igual manera puede ser de utilidad en procesos de control de inventarios, logística, sistemas de seguridad y control de acceso., [EN] This paper presents an RFID reading system for detecting and determining the direction of movement of radio frequency identification (RFID) tags installed in vehicles. This system focuses on the adaptation of secondary radar technology, specifically, the application of monopulse techniques used in SSR (Secondary Surveillance Radar), to the reading antenna. The monopulse antenna is integrated into passive RFID readers that operate in the 915 MHz ISM band (Industrial, Scientific and Medical) for Intelligent Transport Systems (ITS) applications. The system provides the direction of movement of an object that has an RFID tag installed, as well as the reading of the unique code of the tag, by means of a single monopulse antenna and RFID interrogator and a phase detection system that filters the signals received by the antenna and identifies the polarity change in the signal voltage which allows determining the direction of movement of the tag. The system is proposed for applications of Intelligent Transport Systems (ITS), similarly it can be useful in processes of inventory control, logistics, security systems and access control

[ES] En este trabajo se presenta un sistema de lectura RFID para la detección y determinación de la dirección de movimiento de etiquetas de identificación por radiofrecuencia (RFID) instaladas en vehículos. Este sistema se centra en la adaptación de tecnología de radares secundarios, específicamente, la aplicación de técnicas monopulso utilizados en SSR (Radar Secundario de Vigilancia), a la antena de lectura. La antena monopulso se integra en los lectores RFID pasivos que funcionan en la banda ISM de 915 MHz (Industrial, Scientific and Medical) para aplicaciones de Sistemas Inteligentes de Transporte (ITS). El sistema proporciona la dirección de movimiento de un objeto que cuenta con una etiqueta RFID instalada, así como la lectura del código único de la etiqueta, por medio de una única antena monopulso e interrogador RFID y un sistema de detección de fase que filtra las señales recibidas por la antena e identifica el cambio de polaridad en el voltaje de la señal lo que permite determinar el sentido de movimiento de la etiqueta. El sistema se propone para aplicaciones de Sistemas Inteligentes de Transporte (ITS), de igual manera puede ser de utilidad en procesos de control de inventarios, logística, sistemas de seguridad y control de acceso., [EN] This paper presents an RFID reading system for detecting and determining the direction of movement of radio frequency identification (RFID) tags installed in vehicles. This system focuses on the adaptation of secondary radar technology, specifically, the application of monopulse techniques used in SSR (Secondary Surveillance Radar), to the reading antenna. The monopulse antenna is integrated into passive RFID readers that operate in the 915 MHz ISM band (Industrial, Scientific and Medical) for Intelligent Transport Systems (ITS) applications. The system provides the direction of movement of an object that has an RFID tag installed, as well as the reading of the unique code of the tag, by means of a single monopulse antenna and RFID interrogator and a phase detection system that filters the signals received by the antenna and identifies the polarity change in the signal voltage which allows determining the direction of movement of the tag. The system is proposed for applications of Intelligent Transport Systems (ITS), similarly it can be useful in processes of inventory control, logistics, security systems and access control

Frequency-domain diffuse optical imaging (fd-DOI) systems require accurate phase and amplitude measurement of the modulating signal for precise calculation of optical properties of a medium. To reach this accuracy, the current time-resolved DOI methods are prohibitively complex, bulky, and expensive, and generally not compatible with the vision of compact wearable devices. In this dissertation, for the first time, a complete fd-DOI transceiver unit is implemented on a chip. Using only standard CMOS technology to reduce the cost, this transceiver paves the way for complete integration of a time-resolved DOI SoC. Novel methods for measuring phase and amplitude are introduced to enable accurate measurement over more than a decade of frequencies and 60 dB input dynamic range. The systems reaches an optical sensitivity of -57 dBm at 400 MHz modulation frequency with phase and amplitude measurement accuracy of 2 degree and 1dB, respectively. Works like this along with the advances in the vertical cavity surface emitting lasers (VCSELs) and CMOS-integrated photodiodes will enable the development of new methods and devices with the accuracy, precision, and power of time-resolved techniques, but the simplicity, low cost, and wearability of CW devices.

Frequency-domain diffuse optical imaging (fd-DOI) systems require accurate phase and amplitude measurement of the modulating signal for precise calculation of optical properties of a medium. To reach this accuracy, the current time-resolved DOI methods are prohibitively complex, bulky, and expensive, and generally not compatible with the vision of compact wearable devices. In this dissertation, for the first time, a complete fd-DOI transceiver unit is implemented on a chip. Using only standard CMOS technology to reduce the cost, this transceiver paves the way for complete integration of a time-resolved DOI SoC. Novel methods for measuring phase and amplitude are introduced to enable accurate measurement over more than a decade of frequencies and 60 dB input dynamic range. The systems reaches an optical sensitivity of -57 dBm at 400 MHz modulation frequency with phase and amplitude measurement accuracy of 2 degree and 1dB, respectively. Works like this along with the advances in the vertical cavity surface emitting lasers (VCSELs) and CMOS-integrated photodiodes will enable the development of new methods and devices with the accuracy, precision, and power of time-resolved techniques, but the simplicity, low cost, and wearability of CW devices.

Secure chips are in permanent risk of attacks. Physical attacks usually start removing part of the package and accessing the dice by different means: laser shots, electrical or electromagnetic probes, etc. Doing this from the backside of the chip gives some advantages since no metal layers interfere between the hacker and the signals of interest. The bulk silicon is thinned from hundreds to some tens of micrometers in order to improve the performance of the attack. In this paper a backside polishing detector is presented that is sensitive to the thickness of the bulk silicon existing below the transistors, a numerical signature is generated which is related to this. The detector implements built-in self-surveillance techniques which protect it from being tampered., Postprint (published version)

Frequency-domain diffuse optical spectroscopy systems require accurate phase measurement for precise calculation of optical properties of a medium. Different phase detectors and their drawbacks are examined and it is shown how the non-idealities in conventional phase detectors give rise to nonlinearities in the average voltage vs. phase characteristics. A novel circuit for precise phase detection between two signals with the same frequency is presented. The proposed circuit makes use of a pair of XNOR-type phase detectors, to which signal and quadrature reference clocks are applied. A decision circuit then selects which of the two XNORs is used for the output, which guarantees that the circuit will be well within its linear region. All the blocks are designed and simulated in 0.18 micron standard CMOS.

A 2x-oversampling 25Gbps clock and data recovery (CDR) circuit is proposed that employs a charge-based, zero-crossing linearizing phase detector (ZCL-PD). This technique linearizes the conventional bang-bang CDR system, resulting in low quantization jitter, improved loop bandwidth, and improved input sensitivity. To minimize the power consumption, an injection-locked inverter-based 1: 2 divider reduces CML clocking power while maintaining low jitter. The 65nm-CMOS test-chip measurements demonstrate error-free operation for PRBS-7 and PRBS-31, an 120mV differential input sensitivity, a 9MHz jitter transfer bandwidth, 1.08ps/9.63ps (rms/pk-pk) of recovered clock jitter, and 65mW of power consumption.

A 2x-oversampling 25Gbps clock and data recovery (CDR) circuit is proposed that employs a charge-based, zero-crossing linearizing phase detector (ZCL-PD). This technique linearizes the conventional bang-bang CDR system, resulting in low quantization jitter, improved loop bandwidth, and improved input sensitivity. To minimize the power consumption, an injection-locked inverter-based 1: 2 divider reduces CML clocking power while maintaining low jitter. The 65nm-CMOS test-chip measurements demonstrate error-free operation for PRBS-7 and PRBS-31, an 120mV differential input sensitivity, a 9MHz jitter transfer bandwidth, 1.08ps/9.63ps (rms/pk-pk) of recovered clock jitter, and 65mW of power consumption.

Frequency-domain diffuse optical spectroscopy systems require accurate phase measurement for precise calculation of optical properties of a medium. Different phase detectors and their drawbacks are examined and it is shown how the non-idealities in conventional phase detectors give rise to nonlinearities in the average voltage vs. phase characteristics. A novel circuit for precise phase detection between two signals with the same frequency is presented. The proposed circuit makes use of a pair of XNOR-type phase detectors, to which signal and quadrature reference clocks are applied. A decision circuit then selects which of the two XNORs is used for the output, which guarantees that the circuit will be well within its linear region. All the blocks are designed and simulated in 0.18 micron standard CMOS.

A 2x-oversampling 25Gbps clock and data recovery (CDR) circuit is proposed that employs a charge-based, zero-crossing linearizing phase detector (ZCL-PD). This technique linearizes the conventional bang-bang CDR system, resulting in low quantization jitter, improved loop bandwidth, and improved input sensitivity. To minimize the power consumption, an injection-locked inverter-based 1: 2 divider reduces CML clocking power while maintaining low jitter. The 65nm-CMOS test-chip measurements demonstrate error-free operation for PRBS-7 and PRBS-31, an 120mV differential input sensitivity, a 9MHz jitter transfer bandwidth, 1.08ps/9.63ps (rms/pk-pk) of recovered clock jitter, and 65mW of power consumption.

Изложены основные принципы реографии, и поставлена задача модификации его аппаратного обеспечения на основе анализа биологических свойств и процессов, которые происходят в теле человека. Разработана схема реографического измерителя с возможностью регистрации разности фаз между зондирующим и регистрируемым сигналом; обосновано применение регистрации разности фаз; рассмотрены возможности современных реографов с примерами; приведены методы обработки реографического сигнала. Библ. 6, рис. 4, табл. 1., У роботі розглянуто метод реографії, і поставлена задача модифікації його апаратного забезпечення на основі аналізу біологічних властивостей і процесів, які відбуваються в тілі людини. Розроблено схему реографічного вимірювача з можливістю реєстрації різниці фаз між зондувальним і реєстрованим сигналом; обгрунтовано застосування реєстрації різниці фаз; розглянуті можливості сучасних реографії з прикладами; наведені методи обробки реографічного сигналу. Бібл. 6, рис. 4, табл. 1., This paper deals with the principles of the rheography method, which is an effective method of qualitative and quantitative diagnostics of the human body, and the modification of its hardware based on the analysis of biological properties and processes that occur in the body. Based on this analysis, a scheme rheographic to measure the phase difference between the probe and the measured signals is proposed in the article; application of the registration of the phase difference is justified; consider the possibilities of modern rheographs with examples; methods of signal processing rheographic signal are shown. Reference 6, figures 4, tables 1.

In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48 μW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13 μm CMOS technology. Dissipating 0.26 mW from a 1.2 V supply, the fabricated PLL can track signals between 1.62 and 2.49 GHz. For receiver applications, the energy per bit of the receiver is only 0.26 nJ making it attractive for low power applications including wireless sensor networks. © 2010 Elsevier Ltd.

Розглянуто пристрій для збільшення тривалості радіосигналів способом фазового узгодження частоти заповнення за рахунок змінного часу затримки для збільшення точності виміру. Наведено результати експериментального дослідження точності виміру приладу.

The device for The increase of duration of radio signals is considered by the method of phase concordance of frequency of filling due to changeable time of delay for the increase of measuring exactness. The results of experimental research of exactness of measuring of device are resulted., Рассмотрен прибор для увеличения длительности радиосигналов способом фазового согласования частоты заполнения за счет изменяемого времени задержки для увеличения точности измерения. Приведены результаты экспериментального исследования точности измерения прибора., Розглянуто пристрій для збільшення тривалості радіосигналів способом фазового узгодження частоти заповнення за рахунок змінного часу затримки для збільшення точності виміру. Наведено результати експериментального дослідження точності виміру приладу.

Operation of the phase detector designed to work with microwave frequency signals in intense magnetic fields., Рассмотрена работа магниторезистивного фазового детектора, предназначенного для работы с сигналами СВЧ диапазона в сильных магнитных полях., Розглянута робота магніторезистивного фазового детектора призначеного для роботи з сигналами НВЧ діапазону у сильних магнітних полях.

Розглянута робота магніторезистивного фазового детектора призначеного для роботи з сигналами НВЧ діапазону у сильних магнітних полях.

In this paper author describes the phase detector designed to work with microwave frequency signals. This device differs from present nowadays in such way that it has been made not from semiconductor elements (diodes) but from thin magnetoresistive films. The author describes advantages of usage such detectors in waveguide technique., В работе рассматривается фазовый детектор, предназначенный для работы с сигналами СВЧ диапазона, который отличается от существующих тем, что он выполнен не на полупроводниковых элементах (диодах) а на тонких магниторезистивных пленках. Приводятся преимущества таких детекторов., У роботі розглядається фазовий детектор призначений для роботи з сигналами НВЧ діапазону, який відрізняється від існуючих тим, що він виконаний не напівпровідникових елементах (діодах) а на тонких магніторезистивних плівках. Наводяться переваги застосування таких детекторів у хвилеводній техніці.

У роботі розглядається фазовий детектор призначений для роботи з сигналами НВЧ діапазону, який відрізняється від існуючих тим, що він виконаний не напівпровідникових елементах (діодах) а на тонких магніторезистивних плівках. Наводяться переваги застосування таких детекторів у хвилеводній техніці.

A novel strain gage for the measurement of soil deformation is introduced. The gage is based on the principle that the change in the length of a coil is linearly related to the change in its inductance. The gage measures a wide range of strains and can be easily installed on a soil specimen in any direction; therefore, it is particularly suitable for the measurement of deformations of in situ subsurface soil. This paper reports the principle and the characteristics of the gage. A discussion on further improvements is also given.

A novel strain gage for the measurement of soil deformation is introduced. The gage is based on the principle that the change in the length of a coil is linearly related to the change in its inductance. The gage measures a wide range of strains and can be easily installed on a soil specimen in any direction; therefore, it is particularly suitable for the measurement of deformations of in situ subsurface soil. This paper reports the principle and the characteristics of the gage. A discussion on further improvements is also given.

A novel strain gage for the measurement of soil deformation is introduced. The gage is based on the principle that the change in the length of a coil is linearly related to the change in its inductance. The gage measures a wide range of strains and can be easily installed on a soil specimen in any direction; therefore, it is particularly suitable for the measurement of deformations of in situ subsurface soil. This paper reports the principle and the characteristics of the gage. A discussion on further improvements is also given.

Práce se zabývá návrhem FM modulačních řetězců a jejich dílčích obvodů, jejichž konstrukce je založena na analogových násobičkách vyrobených v procesu TSCM 0.18 m 1.8 V. Jeden řetězec pracuje s obdélníkovou nosnou a druhý s harmonickou nosnou vlnou. Základní kmitočet nosné je 100 kHz a základní testovací modulační signál 1 kHz harmonického průběhu. Demodulátory jsou postavené na principu smyčky fázového závěsu a cílem práce je ověřit funkčnost takovéto smyčky a zjistit její limitní vlastnosti. Práce obsahuje také grafické výstupy z vývojového balíčku Cadence Virtuoso, ve kterém byly provedeny všechny simulace., The work deals with the design of FM modulation chains and their sub-circuits, which construction is based on analog multipliers produced in the TSCM process 0.18 m 1.8 V. One chain operate with a rectangular carrier and the other one with a harmonic carrier wave. The basic carrier frequency is 100 kHz, and the basic test modulation signal is 1 kHz harmonic waveform. Demodulators are built on the principle of the phase-locked loop, and the aim of the work is to verify the functionality of such a loop and to determine its limiting properties. The work also contains graphical outputs from the Cadence Virtuoso development package, in which all simulations were performed.

Práce se zabývá návrhem FM modulačních řetězců a jejich dílčích obvodů, jejichž konstrukce je založena na analogových násobičkách vyrobených v procesu TSCM 0.18 m 1.8 V. Jeden řetězec pracuje s obdélníkovou nosnou a druhý s harmonickou nosnou vlnou. Základní kmitočet nosné je 100 kHz a základní testovací modulační signál 1 kHz harmonického průběhu. Demodulátory jsou postavené na principu smyčky fázového závěsu a cílem práce je ověřit funkčnost takovéto smyčky a zjistit její limitní vlastnosti. Práce obsahuje také grafické výstupy z vývojového balíčku Cadence Virtuoso, ve kterém byly provedeny všechny simulace., The work deals with the design of FM modulation chains and their sub-circuits, which construction is based on analog multipliers produced in the TSCM process 0.18 m 1.8 V. One chain operate with a rectangular carrier and the other one with a harmonic carrier wave. The basic carrier frequency is 100 kHz, and the basic test modulation signal is 1 kHz harmonic waveform. Demodulators are built on the principle of the phase-locked loop, and the aim of the work is to verify the functionality of such a loop and to determine its limiting properties. The work also contains graphical outputs from the Cadence Virtuoso development package, in which all simulations were performed.

Tato práce se zabývá návrhem smyčky fázového závěsu. V teoretické části je popsán její princip. V praktické části je podrobný matematický popis, volba různých bloků, výpočet návrhu a optimalizace výsledného řešení. Navržené řešení je simulováno a výsledky jsou komentovány., This work is dealing with phase lock loop design. In the theoretical part is principal description. In the practical part is detailed mathematical description, choice of various blocks, design calculation and optimalization of final solution. Designed solution is simulated and final result are commented.

Tato práce se zabývá návrhem smyčky fázového závěsu. V teoretické části je popsán její princip. V praktické části je podrobný matematický popis, volba různých bloků, výpočet návrhu a optimalizace výsledného řešení. Navržené řešení je simulováno a výsledky jsou komentovány., This work is dealing with phase lock loop design. In the theoretical part is principal description. In the practical part is detailed mathematical description, choice of various blocks, design calculation and optimalization of final solution. Designed solution is simulated and final result are commented.

Práce se zabývá návrhem FM modulačních řetězců a jejich dílčích obvodů, jejichž konstrukce je založena na analogových násobičkách vyrobených v procesu TSCM 0.18 m 1.8 V. Jeden řetězec pracuje s obdélníkovou nosnou a druhý s harmonickou nosnou vlnou. Základní kmitočet nosné je 100 kHz a základní testovací modulační signál 1 kHz harmonického průběhu. Demodulátory jsou postavené na principu smyčky fázového závěsu a cílem práce je ověřit funkčnost takovéto smyčky a zjistit její limitní vlastnosti. Práce obsahuje také grafické výstupy z vývojového balíčku Cadence Virtuoso, ve kterém byly provedeny všechny simulace., The work deals with the design of FM modulation chains and their sub-circuits, which construction is based on analog multipliers produced in the TSCM process 0.18 m 1.8 V. One chain operate with a rectangular carrier and the other one with a harmonic carrier wave. The basic carrier frequency is 100 kHz, and the basic test modulation signal is 1 kHz harmonic waveform. Demodulators are built on the principle of the phase-locked loop, and the aim of the work is to verify the functionality of such a loop and to determine its limiting properties. The work also contains graphical outputs from the Cadence Virtuoso development package, in which all simulations were performed.

Tato práce se zabývá návrhem smyčky fázového závěsu. V teoretické části je popsán její princip. V praktické části je podrobný matematický popis, volba různých bloků, výpočet návrhu a optimalizace výsledného řešení. Navržené řešení je simulováno a výsledky jsou komentovány., This work is dealing with phase lock loop design. In the theoretical part is principal description. In the practical part is detailed mathematical description, choice of various blocks, design calculation and optimalization of final solution. Designed solution is simulated and final result are commented.

Tato práce se zabývá návrhem smyčky fázového závěsu. V teoretické části je popsán její princip. V praktické části je podrobný matematický popis, volba různých bloků, výpočet návrhu a optimalizace výsledného řešení. Navržené řešení je simulováno a výsledky jsou komentovány., This work is dealing with phase lock loop design. In the theoretical part is principal description. In the practical part is detailed mathematical description, choice of various blocks, design calculation and optimalization of final solution. Designed solution is simulated and final result are commented.

Práce se zabývá návrhem FM modulačních řetězců a jejich dílčích obvodů, jejichž konstrukce je založena na analogových násobičkách vyrobených v procesu TSCM 0.18 m 1.8 V. Jeden řetězec pracuje s obdélníkovou nosnou a druhý s harmonickou nosnou vlnou. Základní kmitočet nosné je 100 kHz a základní testovací modulační signál 1 kHz harmonického průběhu. Demodulátory jsou postavené na principu smyčky fázového závěsu a cílem práce je ověřit funkčnost takovéto smyčky a zjistit její limitní vlastnosti. Práce obsahuje také grafické výstupy z vývojového balíčku Cadence Virtuoso, ve kterém byly provedeny všechny simulace., The work deals with the design of FM modulation chains and their sub-circuits, which construction is based on analog multipliers produced in the TSCM process 0.18 m 1.8 V. One chain operate with a rectangular carrier and the other one with a harmonic carrier wave. The basic carrier frequency is 100 kHz, and the basic test modulation signal is 1 kHz harmonic waveform. Demodulators are built on the principle of the phase-locked loop, and the aim of the work is to verify the functionality of such a loop and to determine its limiting properties. The work also contains graphical outputs from the Cadence Virtuoso development package, in which all simulations were performed.

Práce se zabývá návrhem FM modulačních řetězců a jejich dílčích obvodů, jejichž konstrukce je založena na analogových násobičkách vyrobených v procesu TSCM 0.18 m 1.8 V. Jeden řetězec pracuje s obdélníkovou nosnou a druhý s harmonickou nosnou vlnou. Základní kmitočet nosné je 100 kHz a základní testovací modulační signál 1 kHz harmonického průběhu. Demodulátory jsou postavené na principu smyčky fázového závěsu a cílem práce je ověřit funkčnost takovéto smyčky a zjistit její limitní vlastnosti. Práce obsahuje také grafické výstupy z vývojového balíčku Cadence Virtuoso, ve kterém byly provedeny všechny simulace., The work deals with the design of FM modulation chains and their sub-circuits, which construction is based on analog multipliers produced in the TSCM process 0.18 m 1.8 V. One chain operate with a rectangular carrier and the other one with a harmonic carrier wave. The basic carrier frequency is 100 kHz, and the basic test modulation signal is 1 kHz harmonic waveform. Demodulators are built on the principle of the phase-locked loop, and the aim of the work is to verify the functionality of such a loop and to determine its limiting properties. The work also contains graphical outputs from the Cadence Virtuoso development package, in which all simulations were performed.

Práce se zabývá návrhem FM modulačních řetězců a jejich dílčích obvodů, jejichž konstrukce je založena na analogových násobičkách vyrobených v procesu TSCM 0.18 m 1.8 V. Jeden řetězec pracuje s obdélníkovou nosnou a druhý s harmonickou nosnou vlnou. Základní kmitočet nosné je 100 kHz a základní testovací modulační signál 1 kHz harmonického průběhu. Demodulátory jsou postavené na principu smyčky fázového závěsu a cílem práce je ověřit funkčnost takovéto smyčky a zjistit její limitní vlastnosti. Práce obsahuje také grafické výstupy z vývojového balíčku Cadence Virtuoso, ve kterém byly provedeny všechny simulace., The work deals with the design of FM modulation chains and their sub-circuits, which construction is based on analog multipliers produced in the TSCM process 0.18 m 1.8 V. One chain operate with a rectangular carrier and the other one with a harmonic carrier wave. The basic carrier frequency is 100 kHz, and the basic test modulation signal is 1 kHz harmonic waveform. Demodulators are built on the principle of the phase-locked loop, and the aim of the work is to verify the functionality of such a loop and to determine its limiting properties. The work also contains graphical outputs from the Cadence Virtuoso development package, in which all simulations were performed.

The purpose of the research reported on in this paper/ is to demonstrate the effectiveness of a new circuit technique proposed by the author to eliminate the dead-zone anomaly in a digital phase/frequency detector. In addition to demonstrating the elimination of the dead zone, a new loop filter is described. The filter takes advantage of the new phase detector circuit technique so as to simultaneously provide both low-level reference sidebands and a lock-up time of one cycle of the reference., http://archive.org/details/lownoisedigitalp1094521410, Approved for public release; distribution is unlimited.

Tato práce se zabývá návrhem smyčky fázového závěsu. V teoretické části je popsán její princip. V praktické části je podrobný matematický popis, volba různých bloků, výpočet návrhu a optimalizace výsledného řešení. Navržené řešení je simulováno a výsledky jsou komentovány., This work is dealing with phase lock loop design. In the theoretical part is principal description. In the practical part is detailed mathematical description, choice of various blocks, design calculation and optimalization of final solution. Designed solution is simulated and final result are commented.

Tato práce se zabývá návrhem smyčky fázového závěsu. V teoretické části je popsán její princip. V praktické části je podrobný matematický popis, volba různých bloků, výpočet návrhu a optimalizace výsledného řešení. Navržené řešení je simulováno a výsledky jsou komentovány., This work is dealing with phase lock loop design. In the theoretical part is principal description. In the practical part is detailed mathematical description, choice of various blocks, design calculation and optimalization of final solution. Designed solution is simulated and final result are commented.