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The Physical Unclonable Function (PUF) is a promising hardware security primitive because of its inherent uniqueness and low cost. To extract the device-specific variation from delay-based strong PUFs, complex routing constraints are imposed to achieve symmetric path delays; and systematic variations can severely compromise the uniqueness of the PUF. In addition, the metastability of the arbiter circuit of an Arbiter PUF can also degrade the quality of the PUF due to the induced instability. In this paper we propose a novel strong UNBIAS PUF that can be implemented purely by Register Transfer Language (RTL), such as verilog, without imposing any physical design constraints or delay characterization effort to solve the aforementioned issues. Efficient inspection bit prediction models for unbiased response extraction are proposed and validated. Our experimental results of the strong UNBIAS PUF show 5.9% intra-Fractional Hamming Distance (FHD) and 45.1% inter-FHD on 7 Field Programmable Gate Array (FPGA) boards without applying any physical layout constraints or additional XOR gates. The UNBIAS PUF is also scalable because no characterization cost is required for each challenge to compensate the implementation bias. The averaged intra-FHD measured at worst temperature and voltage variation conditions is 12%, which is still below the margin of practical Error Correction Code (ECC) with error reduction techniques for PUFs.

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