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This paper presents a co-design of a 10-bit SAR ADC and its front-end filter. Because the SAR ADC works as a discrete-time data converter, its input signal only needs to be accurate at its sampling moment. Therefore, the filter can be switched off in the ADC conversion phase to save power. To reduce the start-up time when the filter is activated again, a low-power auxiliary amplifier is used in the ADC conversion phase to maintain the filter output roughly. A 10-bit 10 MS/s SAR ADC with such a duty-cycled multiple feedback filter is fabricated in a 65 nm CMOS technology. The filter power has been reduced by 36% thanks to the proposed duty-cycled operation. The prototype achieves 8.3 ENOB and 59.3 dB SFDR at low input frequencies, and it has 40 dB suppression at the Nyquist input frequency, while consuming 91.1 µ W.

This letter presents a dynamic resistive temperature sensor for IoT ambient temperature monitoring applications. The sensor integrates on-chip analog offset, gain, and nonlinearity correction techniques with state-of-the-art power and size performance. By shifting the reset phase of the ADC, analog offset correction is realized. By adding programmable capacitors, gain errors are corrected. By presetting and resetting a small capacitor array, the systematic nonlinearity error is mitigated. A piecewise linear approximation is adopted to reduce overhead. The temperature sensor achieves +0.7°C/-0.6°C accuracy with 2.98 pJ/conversion and 0.0023 mm2, including all corrections, resulting in a resolution FoM of 0.66 pJ K2.

This paper reviews several examples of ultra low power sensor interfaces for IoT applications. In such applications, the sensing operation is often performed at a relatively low frequency, and sometimes it is heavily duty-cycled, or it should be triggered by particular events or thresholds. The paper reviews why dynamic sensor interface architectures are a good choice in this context, and gives several design examples that can operate dynamically and that can be triggered by a single clock pulse. Suitable ADC design strategies are explained, and two exemplary sensor interfaces are described: a capacitive sensor interface, and a resistor-based temperature sensor interface including analog correction techniques. Both designs are reviewed and the main features in terms of efficiency and performance are discussed.

Nowadays, many battery-operated SoCs for loT and environmental monitoring applications are equipped with temperature sensors. In these miniaturized systems, power and area are two critical concerns. One challenge for temperature sensors is that they are sensitive to process corners and random mismatch. Generally, a 2-point trim and systematic non-linear error removal are required, especially for resistor-based sensing front-ends with two types of resistors, whose spread is partially uncorrelated [1], [2]. These corrections are done off-chip and digitally in most publications. In particular for low power sensors, they may consume more power and area than the sensor itself when integrated on-chip [3]. This work presents a resistive temperature sensor that integrates on-chip analog offset, gain and non-linearity correction techniques, while keeping state-of-the-art power and size performance. The prototype consumes 2.98pJ/conversion with an area of 0. 0023textmm 2 including all the correction techniques and achieves +0.7/-0.6 circC inaccuracy.

The sampling noise cancellation (SNC) technique has been applied to different discrete-time circuits in recent literature, but the cost of this technique has not been well studied. This paper gives a detailed analysis of the SNC approach in a track-and-hold amplifier (THA). Closed-form expressions are derived for each noise source in the THA during the sampling phase and are verified by simulations. The analysis shows that while the sampling noise can be cancelled, the noise from the extra amplifier and switches can become dominant and even outweigh the benefits from SNC. Therefore, the SNC technique should be used with attention to the trade-offs, as described in this paper.

This work presents a 14-bit oversampled successive-approximation-register (SAR) analog-to-digital converter (ADC) with mismatch error shaping (MES) and pre-comparison techniques. A pre-comparison technique is proposed to solve the over-range problem caused by MES. With MES and pre-comparison, the digital-to-analog converter (DAC) mismatch error can be first-order shaped, while a full input range is maintained. Besides, data-driven noise reduction and chopping techniques are combined to reduce the comparator noise efficiently. The prototype in 65-nm CMOS achieves 84.5-dB signal-to-noise-and-distortion ratio (SNDR) and 103-dB spurious-free dynamic range (SFDR) in a 4-kHz bandwidth, with a power consumption of 0.98 mu {W} from a single 0.8-V supply and an area of 0.033 mm2, resulting in a Schreier figure of merit (FoM) of 180.6 dB and a Walden FoM of 8.9 fJ/conversion-step, respectively. Among ADCs with above 100-dB SFDR, this is the smallest design without calibration and the only sub- mu {W} and sub-1-V design. These features make it suitable for high-resolution and low-cost applications.

This brief presents four small-area SAR ADCs with a resolution from 8 to 11 bits. Two area-saving techniques are utilized. First, the DAC layout is implemented with custom designed unit-length capacitors, which are optimized for each resolution to minimize the chip area. Second, dynamic logic is applied to the 8-bit design to further reduce the number of transistors and save area. Fabricated in 65 nm CMOS, the 8/9/10/11-bit SAR ADCs only occupy 20times 21,,mu text{m} , 20times 36,,mu text{m} , 36times 36,,mu text{m} and 36times 36,,mu text{m} , respectively. At 10 MHz sampling rate, their measured ENOB is 7.5, 8.3, 9.1 and 9.8 bits with an SFDR of 65.4 dB, 67.4 dB, 78.0 dB and 76.5 dB, respectively. Compared to prior-art, these designs achieve the smallest areas for the achieved ENOBs.

This work presents a reconfigurable delay and redundancy technique, which relaxes the reference driver requirements for a charge-redistribution SAR ADC. By selectively adding delay to the most critical SAR cycle, the overall speed of the ADC is only slightly degraded, while the output impedance of the driver or the amount of decoupling capacitance can be reduced substantially. In a simulated 10-bit 10 MS/s SAR ADC prototype, the proposed technique reduces the decoupling capacitance by 16× while maintaining 59.2 dB SNDR and 71.2 dB SFDR at a power consumption of 32 mu mathrm{W}. The estimated area is 0.002 mm2 including decoupling capacitors.

This paper presents the first continuous-time (CT) noise-shaping SAR (NS-SAR) ADC. Different from the prior discrete-time (DT) NS-SAR ADCs in literature, this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT-operated SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty-cycled. Fabricated in 65 nm CMOS, the prototype achieves 77 dB peak SNDR within 62.5 kHz bandwidth while consuming 13.5 W, and it provides 15 dB anti-aliasing in the alias band.

This paper presents a duty-cycled input driver for a SAR ADC. Being a discrete-time system, the SAR ADC requires an accurate input signal only at its sampling moment. This motivates the use of a duty-cycled input driver which can be turned off during the conversion phase to save power. In this way, the power consumption of the SAR ADC together with its input driver becomes fully dynamic. This idea is applied to a 10-bit 4 MS/s SAR ADC with unity-gain input drivers. Fabricated in 65 nm CMOS, the prototype achieves 8.9 ENOB and 69.9 dB SFDR while consuming 35.0 µW. This leads to a Walden FoM of 18.3 fJ/conversion-step for the ADC including driver.

This paper presents a dynamic temperature sensor in 65nm CMOS with on-chip analog gain and offset correction for low power systems. By shifting the reset phase of the N-bit ADC, offset correction with a range of \pm 2^{(N-1)} LSB is realized. Fine tuning capacitors are introduced to improve the offset correction accuracy to 0.5LSB. By adding programmable parasitic capacitors, gain errors up to 6.3% can be compensated. Thanks to the proposed analog correction techniques, the gain errors are reduced to 0.73% and the offsets are reduced to 0.5LSB. This sensor consumes 2.74pJ per conversion and only occupies an area of 0.0018 mm2 including the extra correction techniques. It has an RMS resolution of 0.47K, leading to a FoM of 0.6 pJ.K2.

This brief presents a 10.5-bit 10 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) with 1.5times input range (IR). By pre-setting and resetting the most significant bit (MSB) of the digital-to-analog converter (DAC) to shift the input signal accordingly, the input range of the ADC is enhanced by a factor of 1.5. This effectively relaxes the noise requirement and thus improves the power efficiency of the ADC. The prototype implemented in 65-nm CMOS technology achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.37 dB and a spurious-free dynamic range (SFDR) of 82.2 dB. It consumes 18.65~mu text{W} at 10 MS/s with a 0.8V supply and only occupies an area of 0.0013 mm2. The resulting Walden figure of merit (FoM _{W} ) is 2.2 fJ/conversion-step.

Photoacoustic (PA) imaging has been widely applied in both preclinical and clinical applications. With a significantly increasing number of data acquisition channels, fast and high-quality image reconstruction for real-time PA imaging is an open challenge in this community. In this paper, we propose a FPGA-accelerated method to achieve a much faster image reconstruction speed by 20~60 times compared with using CPU, with much-reduced system cost and power budget, from dozens of Watt (CPU) to 1~2 Watt (FPGA). Equivalently, the energy efficiency ratio (EER) is improved by ~1000 times. This FPGA acceleration method can be easily adapted to the most widely used algorithms, such as delay-and-sum (DAS) and its variants (e.g. DMAS, DAS-CF). We have performed in-vivo human finger experiments to demonstrate the feasibility and potential of the proposed method. To our best knowledge, this is the first study of accelerating PA image reconstruction based on FPGA platform.

The sampling noise cancellation (SNC) technique has been applied to different discrete-time circuits in recent literature, but the cost of this technique has not been well studied. This paper gives a detailed analysis of the SNC approach in a track-and-hold amplifier (THA). Closed-form expressions are derived for each noise source in the THA during the sampling phase and are verified by simulations. The analysis shows that while the sampling noise can be cancelled, the noise from the extra amplifier and switches can become dominant and even outweigh the benefits from SNC. Therefore, the SNC technique should be used with attention to the trade-offs, as described in this paper.

This work presents a 14-bit oversampled successive-approximation-register (SAR) analog-to-digital converter (ADC) with mismatch error shaping (MES) and pre-comparison techniques. A pre-comparison technique is proposed to solve the over-range problem caused by MES. With MES and pre-comparison, the digital-to-analog converter (DAC) mismatch error can be first-order shaped, while a full input range is maintained. Besides, data-driven noise reduction and chopping techniques are combined to reduce the comparator noise efficiently. The prototype in 65-nm CMOS achieves 84.5-dB signal-to-noise-and-distortion ratio (SNDR) and 103-dB spurious-free dynamic range (SFDR) in a 4-kHz bandwidth, with a power consumption of 0.98 mu {W} from a single 0.8-V supply and an area of 0.033 mm2, resulting in a Schreier figure of merit (FoM) of 180.6 dB and a Walden FoM of 8.9 fJ/conversion-step, respectively. Among ADCs with above 100-dB SFDR, this is the smallest design without calibration and the only sub- mu {W} and sub-1-V design. These features make it suitable for high-resolution and low-cost applications.

This paper presents a low-power and high-linearity noise-shaping SAR ADC that employs a duty-cycled amplifier and a mismatch error shaping technique. The power-efficient duty-cycled amplifier with 18x gain and two passive integrators provide 2nd-order noise shaping to improve in-band noise attenuation. Mismatch error shaping with a two-level digital prediction scheme is used to 1st-order shape the capacitive DAC mismatch errors without sacrificing the input signal range. The proposed ADC is fabricated in 65 nm CMOS technology and achieves 80 dB peak SNDR and 98 dB peak SFDR in a 31.25 kHz bandwidth, leading to a Schreier FoM of 176.3 dB.

This work presents a simplex and a full-duplex digital communication interface in 65 nm CMOS that enhance the energy efficiency of chip-to-chip digital communication in low-speed low-power systems, e.g., for Internet-of-Things applications. A capacitive fully dynamic simplex interface is proposed first. A self-interference cancellation network is then applied to achieve full-duplex operation. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5. 10^{-12}. The simplex and full-duplex interfaces achieve an energy consumption of 0.38 and 1.2 pJ/b, respectively (with 19 pF load). The simplex interface achieves a power reduction of 2\times to 27\times compared to conventional low-voltage CMOS for data rates from 10 kb/s to 50 Mb/s. The full-duplex interface achieves a power reduction of 5\times to 11\times for data rates from 100 kb/s to 50 Mb/s.

This work presents a simplex and a full-duplex digital communication interface in 65 nm CMOS that enhance the energy efficiency of chip-to-chip digital communication in low-speed low-power systems, e.g., for Internet-of-Things applications. A capacitive fully dynamic simplex interface is proposed first. A self-interference cancellation network is then applied to achieve full-duplex operation. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5. 10^{-12}. The simplex and full-duplex interfaces achieve an energy consumption of 0.38 and 1.2 pJ/b, respectively (with 19 pF load). The simplex interface achieves a power reduction of 2\times to 27\times compared to conventional low-voltage CMOS for data rates from 10 kb/s to 50 Mb/s. The full-duplex interface achieves a power reduction of 5\times to 11\times for data rates from 100 kb/s to 50 Mb/s.

An understanding of nanocrystal shape evolution is significant for the design, synthesis, and applications of nanocrystals with surface-enhanced properties such as catalysis or plasmonics. Surface adsorbates that are selectively attached to certain facets may strongly affect the atomic pathways of nanocrystal shape development. However, it is a great challenge to directly observe such dynamic processes in situ with a high spatial resolution. Here, we report the anomalous shape evolution of Ag2O2 nanocrystals modulated by the surface adsorbates of Ag clusters during electron beam etching, which is revealed through in situ transmission electron microscopy (TEM). In contrast to the Ag2O2 nanocrystals without adsorbates, which display the near-equilibrium shape throughout the etching process, Ag2O2 nanocrystals with Ag surface adsorbates show distinct facet development during etching by electron beam irradiation. Three stages of shape changes are observed: a sphere-to-a cube transformation, side etching of a cuboid, and bottom etching underneath the surface adsorbates. We find that the Ag adsorbates modify the Ag2O2 nanocrystal surface configuration by selectively capping the junction between two neighboring facets. They prevent the edge atoms from being etched away and block the diffusion path of surface atoms. Our findings provide critical insights into the modulatory function of surface adsorbates on the shape control of nanocrystals.

An understanding of nanocrystal shape evolution is significant for the design, synthesis, and applications of nanocrystals with surface-enhanced properties such as catalysis or plasmonics. Surface adsorbates that are selectively attached to certain facets may strongly affect the atomic pathways of nanocrystal shape development. However, it is a great challenge to directly observe such dynamic processes in situ with a high spatial resolution. Here, we report the anomalous shape evolution of Ag2O2 nanocrystals modulated by the surface adsorbates of Ag clusters during electron beam etching, which is revealed through in situ transmission electron microscopy (TEM). In contrast to the Ag2O2 nanocrystals without adsorbates, which display the near-equilibrium shape throughout the etching process, Ag2O2 nanocrystals with Ag surface adsorbates show distinct facet development during etching by electron beam irradiation. Three stages of shape changes are observed: a sphere-to-a cube transformation, side etching of a cuboid, and bottom etching underneath the surface adsorbates. We find that the Ag adsorbates modify the Ag2O2 nanocrystal surface configuration by selectively capping the junction between two neighboring facets. They prevent the edge atoms from being etched away and block the diffusion path of surface atoms. Our findings provide critical insights into the modulatory function of surface adsorbates on the shape control of nanocrystals.

With the development of mobile devices and Internet-of-Things,the demand for low-power circuits has been growing rapidly. The Analog-to-Digital Converter (ADC) is a key building block in these systems. In this work,we review the progress of low-power ADCs over the years in terms of performance and limitations. From these limitations,it can be shown why sometimes very different approaches are used to minimize power consumption. Various state-of-the-art examples will be shown to illustrate the diversity of techniques and ideas within the field. Next,an outlook to the future is given by discussing various unsolved challenges and new opportunities.

The internationalization in higher education is very popular around the word. The United Kingdom has many great universities that are famous and highly ranked around the world, and attract students from different countries. The internationalization in the higher education institutions in the UK is very common, and almost each university has international students and international academic staff. The different educational background and cultural background rich the cultural diversity, however, also bring challenges to international academic staff. Therefore, this paper aims to research the challenges international academic staff face in terms of culture and discuss the influence of that. The paper will choose Chinese academic staff in the Nottingham university as research subjective, since Chinese academic staff are now the top group of international academic staff in the UK, and the state system and educational context are quite different between China and UK. The paper will use semi-structured interview as research method to find the challenges and influence of culture on them.