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The model of membrane computing, also known under the name of P systems, is a bio-inspired large-scale parallel computing paradigm having a good potential for the design of massively parallel algorithms. For its implementation it is very natural to choose hardware platforms that have important inherent parallelism, such as field-programmable gate arrays (FPGAs) or compute unified device architecture (CUDA)-enabled graphic processing units (GPUs). This article performs an overview of all existing approaches of hardware implementation in the area of P systems. The quantitative and qualitative attributes of FPGA-based implementations and CUDA-enabled GPU-based simulations are compared to evaluate the two methodologies.

Implementing the P systems on parallel hardware is a research highlight in bio-inspired computing since the membrane computing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware implementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is particularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding problem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem.

The model of membrane computing, also known under the name of P systems, is a bio-inspired large-scale parallel computing paradigm having a good potential for the design of massively parallel algorithms. For its implementation it is very natural to choose hardware platforms that have important inherent parallelism, such as field-programmable gate arrays (FPGAs) or compute unified device architecture (CUDA)-enabled graphic processing units (GPUs). This article performs an overview of all existing approaches of hardware implementation in the area of P systems. The quantitative and qualitative attributes of FPGA-based implementations and CUDA-enabled GPU-based simulations are compared to evaluate the two methodologies.

Implementing the P systems on parallel hardware is a research highlight in bio-inspired computing since the membrane computing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware implementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is particularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding problem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem.

The model of membrane computing, also known under the name of P systems, is a bio-inspired large-scale parallel computing paradigm having a good potential for the design of massively parallel algorithms. For its implementation it is very natural to choose hardware platforms that have important inherent parallelism, such as field-programmable gate arrays (FPGAs) or compute unified device architecture (CUDA)-enabled graphic processing units (GPUs). This article performs an overview of all existing approaches of hardware implementation in the area of P systems. The quantitative and qualitative attributes of FPGA-based implementations and CUDA-enabled GPU-based simulations are compared to evaluate the two methodologies.

The model of membrane computing, also known under the name of P systems, is a bio-inspired large-scale parallel computing paradigm having a good potential for the design of massively parallel algorithms. For its implementation it is very natural to choose hardware platforms that have important inherent parallelism, such as field-programmable gate arrays (FPGAs) or compute unified device architecture (CUDA)-enabled graphic processing units (GPUs). This article performs an overview of all existing approaches of hardware implementation in the area of P systems. The quantitative and qualitative attributes of FPGA-based implementations and CUDA-enabled GPU-based simulations are compared to evaluate the two methodologies.

Implementing the P systems on parallel hardware is a research highlight in bio-inspired computing since the membrane computing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware implementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is particularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding problem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem.

Implementing the P systems on parallel hardware is a research highlight in bio-inspired computing since the membrane computing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware implementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is particularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding problem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem.

The model of membrane computing, also known under the name of P systems, is a bio-inspired large-scale parallel computing paradigm having a good potential for the design of massively parallel algorithms. For its implementation it is very natural to choose hardware platforms that have important inherent parallelism, such as field-programmable gate arrays (FPGAs) or compute unified device architecture (CUDA)-enabled graphic processing units (GPUs). This article performs an overview of all existing approaches of hardware implementation in the area of P systems. The quantitative and qualitative attributes of FPGA-based implementations and CUDA-enabled GPU-based simulations are compared to evaluate the two methodologies.

The model of membrane computing, also known under the name of P systems, is a bio-inspired large-scale parallel computing paradigm having a good potential for the design of massively parallel algorithms. For its implementation it is very natural to choose hardware platforms that have important inherent parallelism, such as field-programmable gate arrays (FPGAs) or compute unified device architecture (CUDA)-enabled graphic processing units (GPUs). This article performs an overview of all existing approaches of hardware implementation in the area of P systems. The quantitative and qualitative attributes of FPGA-based implementations and CUDA-enabled GPU-based simulations are compared to evaluate the two methodologies.

The model of membrane computing, also known under the name of P systems, is a bio-inspired large-scale parallel computing paradigm having a good potential for the design of massively parallel algorithms. For its implementation it is very natural to choose hardware platforms that have important inherent parallelism, such as field-programmable gate arrays (FPGAs) or compute unified device architecture (CUDA)-enabled graphic processing units (GPUs). This article performs an overview of all existing approaches of hardware implementation in the area of P systems. The quantitative and qualitative attributes of FPGA-based implementations and CUDA-enabled GPU-based simulations are compared to evaluate the two methodologies.

Implementing the P systems on parallel hardware is a research highlight in bio-inspired computing since the membrane computing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware implementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is particularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding problem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem.

Implementing the P systems on parallel hardware is a research highlight in bio-inspired computing since the membrane computing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware implementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is particularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding problem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem.

It is a long-cherished wish to implement numerical P systems (NPS) on a parallel architecture so that its large scale parallelism can be exploited to speedup computation tremendously. FPGA is a reconfigurable hardware in which operations are triggered so synchronized by edge or level of activating signals, making it an eligible platform to implement NPS and its variant, enzymatic numerical P system (ENPS). In this article, a NPS and a ENPS designed as robot controllers are implemented in FPGA, achieving a speedup of 105 comparing to software simulation. FPGA hardened NPS in this research can be regarded as a heterogeneous multicore processor since membranes inside work as processing units which possess different functions. FPGA hardened NPS is imparted universal asynchronous receiver/transmitter (UART) communication ability to push it closer to real-life application. FPGA hardened ENPS consume less hardware resources and power for less complicate membrane structures and processes.

It is a long-cherished wish to implement numerical P systems (NPS) on a parallel architecture so that its large scale parallelism can be exploited to speedup computation tremendously. FPGA is a reconfigurable hardware in which operations are triggered so synchronized by edge or level of activating signals, making it an eligible platform to implement NPS and its variant, enzymatic numerical P system (ENPS). In this article, a NPS and a ENPS designed as robot controllers are implemented in FPGA, achieving a speedup of 105 comparing to software simulation. FPGA hardened NPS in this research can be regarded as a heterogeneous multicore processor since membranes inside work as processing units which possess different functions. FPGA hardened NPS is imparted universal asynchronous receiver/transmitter (UART) communication ability to push it closer to real-life application. FPGA hardened ENPS consume less hardware resources and power for less complicate membrane structures and processes.

It is a long-cherished wish to implement numerical P systems (NPS) on a parallel architecture so that its large scale parallelism can be exploited to speedup computation tremendously. FPGA is a reconfigurable hardware in which operations are triggered so synchronized by edge or level of activating signals, making it an eligible platform to implement NPS and its variant, enzymatic numerical P system (ENPS). In this article, a NPS and a ENPS designed as robot controllers are implemented in FPGA, achieving a speedup of 105 comparing to software simulation. FPGA hardened NPS in this research can be regarded as a heterogeneous multicore processor since membranes inside work as processing units which possess different functions. FPGA hardened NPS is imparted universal asynchronous receiver/transmitter (UART) communication ability to push it closer to real-life application. FPGA hardened ENPS consume less hardware resources and power for less complicate membrane structures and processes.

It is a long-cherished wish to implement numerical P systems (NPS) on a parallel architecture so that its large scale parallelism can be exploited to speedup computation tremendously. FPGA is a reconfigurable hardware in which operations are triggered so synchronized by edge or level of activating signals, making it an eligible platform to implement NPS and its variant, enzymatic numerical P system (ENPS). In this article, a NPS and a ENPS designed as robot controllers are implemented in FPGA, achieving a speedup of 105 comparing to software simulation. FPGA hardened NPS in this research can be regarded as a heterogeneous multicore processor since membranes inside work as processing units which possess different functions. FPGA hardened NPS is imparted universal asynchronous receiver/transmitter (UART) communication ability to push it closer to real-life application. FPGA hardened ENPS consume less hardware resources and power for less complicate membrane structures and processes.

It is a long-cherished wish to implement numerical P systems (NPS) on a parallel architecture so that its large scale parallelism can be exploited to speedup computation tremendously. FPGA is a reconfigurable hardware in which operations are triggered so synchronized by edge or level of activating signals, making it an eligible platform to implement NPS and its variant, enzymatic numerical P system (ENPS). In this article, a NPS and a ENPS designed as robot controllers are implemented in FPGA, achieving a speedup of 105 comparing to software simulation. FPGA hardened NPS in this research can be regarded as a heterogeneous multicore processor since membranes inside work as processing units which possess different functions. FPGA hardened NPS is imparted universal asynchronous receiver/transmitter (UART) communication ability to push it closer to real-life application. FPGA hardened ENPS consume less hardware resources and power for less complicate membrane structures and processes.

Implementing the P systems on parallel hardware is a re- search highlight in bio-inspired computing since the membrane comput- ing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware im- plementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is par- ticularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding prob- lem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem

Implementing the P systems on parallel hardware is a re- search highlight in bio-inspired computing since the membrane comput- ing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware im- plementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is par- ticularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding prob- lem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem

Implementing the P systems on parallel hardware is a re- search highlight in bio-inspired computing since the membrane comput- ing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware im- plementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is par- ticularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding prob- lem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem

Implementing the P systems on parallel hardware is a re- search highlight in bio-inspired computing since the membrane comput- ing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware im- plementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is par- ticularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding prob- lem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem

Implementing the P systems on parallel hardware is a re- search highlight in bio-inspired computing since the membrane comput- ing is a large-scale parallel computing paradigm which have a potential to tremendously speed up the computation. Field-programmable gate arrays (FPGAs) and CUDA-enabled GPUs are the primary hardware which is employed to implement P systems. FPGA-based hardware im- plementations use different strategies considering regions or evolution rules as processing units. This implies the existence of several parallel architectures for FPGAs specially designed to implement P systems. In contrast, the CUDA-enabled GPUs are a pre-defined parallel platform and numerous types of P systems are directly implemented on it. The object distribution problem (choosing which rules will be applied) is the core problem of all hardware implementations. This problem is par- ticularly difficult, because in the general case the model of P systems is non-deterministic and maximally parallel, hence the corresponding prob- lem is NP-hard. Several heuristics were proposed in order to accelerate the process of the computation of the corresponding ruleset. In this article we overview different approaches and designs for hardware implementations of P systems as well as corresponding solutions to the object assignment problem