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The past few years have seen a wave of enthusiasm for serverless computing, and we begin this work by analyzing the marketplace trends and underlying technical factors that have shaped the movement. We find that serverless computing addresses programming challenges in the same class as those that high-level programming languages address, suggesting that serverless computing may be viewed as high-level programming for distributed systems.We next turn our attention to one of the key shortcomings of serverless: the lack of integration between compute and state. We develop FaaSFS, a distributed file system that is compatible with POSIX applications but uses a novel consistency model with relaxed real-time ordering constraints. We call this model externally consistent sequential consistency (ECSC) and use it to scale a pre-existing single-server application to 10,000 serverless processes. We also show that under reasonable assumptions ECSC is indistinguishable from linearizability, a widely accepted strong form of consistency.Lastly, we explore whether serverless computing might lead to the demise of server hardware. By applying Amdahl's law and scaling rules for interconnect costs, we show that applications that rely on coordination protocols are particularly dependent on large servers for scalability. In contrast, those implemented with coordination-free protocols can run well on collections of small, low-cost servers or on disaggregated hardware. These approaches will likely continue to coexist, suggesting that a need for underlying server hardware will remain even as serverless abstractions thrive.

The paper considers various approaches to developing display controller driver software for embedded systems, which usually use System-on-chip (SOC) solutions and real-time operating systems (RTOS). It also describes the main principles and design decisions of the chosen RTOS, such as portability, flexible scheduling, responsiveness, etc., as well as used standards (C language, POSIX 1003.1, ARINC 653). The authors list general operating principles of the display controller hardware including support for several displays and overlays that can be used for displaying multiple video streams on one screen or achieving the effect similar to chroma keying. The proposed method for developing display controller drivers defines the main parameters of the display controller hardware and the steps necessary to show an image on a screen correctly. The meth-od also takes into account the features related to using hardware interrupts and estimating the frequen-cy required for display controller to show an image on a screen correctly with the defined screen mode. Contrary to the known methods, the proposed method takes into account various features of the many real-time operating systems: lack of dedicated API to interact with graphics hardware and resources, seamless access to hardware registers from user space and so on. The paper considers several ap-proaches to debugging software on the target hardware as well as using prototyping systems based on FPGA. Prototyping systems usually introduce additional challenges to debugging, such as low simula-tion speed. The proposed method was tested during the development of the display controller driver for the home made RTOS..

The paper considers various approaches to developing display controller driver software for embedded systems, which usually use System-on-chip (SOC) solutions and real-time operating systems (RTOS). It also describes the main principles and design decisions of the chosen RTOS, such as portability, flexible scheduling, responsiveness, etc., as well as used standards (C language, POSIX 1003.1, ARINC 653). The authors list general operating principles of the display controller hardware including support for several displays and overlays that can be used for displaying multiple video streams on one screen or achieving the effect similar to chroma keying. The proposed method for developing display controller drivers defines the main parameters of the display controller hardware and the steps necessary to show an image on a screen correctly. The meth-od also takes into account the features related to using hardware interrupts and estimating the frequen-cy required for display controller to show an image on a screen correctly with the defined screen mode. Contrary to the known methods, the proposed method takes into account various features of the many real-time operating systems: lack of dedicated API to interact with graphics hardware and resources, seamless access to hardware registers from user space and so on. The paper considers several ap-proaches to debugging software on the target hardware as well as using prototyping systems based on FPGA. Prototyping systems usually introduce additional challenges to debugging, such as low simula-tion speed. The proposed method was tested during the development of the display controller driver for the home made RTOS..

The paper considers various approaches to developing display controller driver software for embedded systems, which usually use System-on-chip (SOC) solutions and real-time operating systems (RTOS). It also describes the main principles and design decisions of the chosen RTOS, such as portability, flexible scheduling, responsiveness, etc., as well as used standards (C language, POSIX 1003.1, ARINC 653). The authors list general operating principles of the display controller hardware including support for several displays and overlays that can be used for displaying multiple video streams on one screen or achieving the effect similar to chroma keying. The proposed method for developing display controller drivers defines the main parameters of the display controller hardware and the steps necessary to show an image on a screen correctly. The meth-od also takes into account the features related to using hardware interrupts and estimating the frequen-cy required for display controller to show an image on a screen correctly with the defined screen mode. Contrary to the known methods, the proposed method takes into account various features of the many real-time operating systems: lack of dedicated API to interact with graphics hardware and resources, seamless access to hardware registers from user space and so on. The paper considers several ap-proaches to debugging software on the target hardware as well as using prototyping systems based on FPGA. Prototyping systems usually introduce additional challenges to debugging, such as low simula-tion speed. The proposed method was tested during the development of the display controller driver for the home made RTOS..

The paper considers various approaches to developing display controller driver software for embedded systems, which usually use System-on-chip (SOC) solutions and real-time operating systems (RTOS). It also describes the main principles and design decisions of the chosen RTOS, such as portability, flexible scheduling, responsiveness, etc., as well as used standards (C language, POSIX 1003.1, ARINC 653). The authors list general operating principles of the display controller hardware including support for several displays and overlays that can be used for displaying multiple video streams on one screen or achieving the effect similar to chroma keying. The proposed method for developing display controller drivers defines the main parameters of the display controller hardware and the steps necessary to show an image on a screen correctly. The meth-od also takes into account the features related to using hardware interrupts and estimating the frequen-cy required for display controller to show an image on a screen correctly with the defined screen mode. Contrary to the known methods, the proposed method takes into account various features of the many real-time operating systems: lack of dedicated API to interact with graphics hardware and resources, seamless access to hardware registers from user space and so on. The paper considers several ap-proaches to debugging software on the target hardware as well as using prototyping systems based on FPGA. Prototyping systems usually introduce additional challenges to debugging, such as low simula-tion speed. The proposed method was tested during the development of the display controller driver for the home made RTOS..

The paper considers various approaches to developing display controller driver software for embedded systems, which usually use System-on-chip (SOC) solutions and real-time operating systems (RTOS). It also describes the main principles and design decisions of the chosen RTOS, such as portability, flexible scheduling, responsiveness, etc., as well as used standards (C language, POSIX 1003.1, ARINC 653). The authors list general operating principles of the display controller hardware including support for several displays and overlays that can be used for displaying multiple video streams on one screen or achieving the effect similar to chroma keying. The proposed method for developing display controller drivers defines the main parameters of the display controller hardware and the steps necessary to show an image on a screen correctly. The meth-od also takes into account the features related to using hardware interrupts and estimating the frequen-cy required for display controller to show an image on a screen correctly with the defined screen mode. Contrary to the known methods, the proposed method takes into account various features of the many real-time operating systems: lack of dedicated API to interact with graphics hardware and resources, seamless access to hardware registers from user space and so on. The paper considers several ap-proaches to debugging software on the target hardware as well as using prototyping systems based on FPGA. Prototyping systems usually introduce additional challenges to debugging, such as low simula-tion speed. The proposed method was tested during the development of the display controller driver for the home made RTOS..

Whereas Perl-compatible regular expression matchers typically exhibit some variation of leftmost-greedy semantics, those conforming to the posix standard are prescribed leftmost-longest semantics. However, the posix standard leaves some room for interpretation, and Fowler and Kuklewicz have done experimental work to confirm differences between various posix matchers. The Boost library has an interesting take on the posix standard, where it maximises the leftmost match not with respect to subexpressions of the regular expression pattern, but rather, with respect to capturing groups. In our work, we provide the first formalisation of Boost semantics, analyze the complexity of regular expression matching when using Boost semantics, and provide efficient algorithms for both online and multipass matching.

The paper considers various approaches to developing display controller driver software for embedded systems, which usually use System-on-chip (SOC) solutions and real-time operating systems (RTOS). It also describes the main principles and design decisions of the chosen RTOS, such as portability, flexible scheduling, responsiveness, etc., as well as used standards (C language, POSIX 1003.1, ARINC 653). The authors list general operating principles of the display controller hardware including support for several displays and overlays that can be used for displaying multiple video streams on one screen or achieving the effect similar to chroma keying. The proposed method for developing display controller drivers defines the main parameters of the display controller hardware and the steps necessary to show an image on a screen correctly. The meth-od also takes into account the features related to using hardware interrupts and estimating the frequen-cy required for display controller to show an image on a screen correctly with the defined screen mode. Contrary to the known methods, the proposed method takes into account various features of the many real-time operating systems: lack of dedicated API to interact with graphics hardware and resources, seamless access to hardware registers from user space and so on. The paper considers several ap-proaches to debugging software on the target hardware as well as using prototyping systems based on FPGA. Prototyping systems usually introduce additional challenges to debugging, such as low simula-tion speed. The proposed method was tested during the development of the display controller driver for the home made RTOS..

Many scientific fields increasingly use high-performance computing (HPC) to process and analyze massive amounts of experimental data while storage systems in today’s HPC environments have to cope with new access patterns. These patterns include many metadata operations, small I/O requests, or randomized file I/O, while general-purpose parallel file systems have been optimized for sequential shared access to large files. Burst buffer file systems create a separate file system that applications can use to store temporary data. They aggregate node-local storage available within the compute nodes or use dedicated SSD clusters and offer a peak bandwidth higher than that of the backend parallel file system without interfering with it. However, burst buffer file systems typically offer many features that a scientific application, running in isolation for a limited amount of time, does not require. We present GekkoFS, a temporary, highly-scalable file system which has been specifically optimized for the aforementioned use cases. GekkoFS provides relaxed POSIX semantics which only offers features which are actually required by most (not all) applications. GekkoFS is, therefore, able to provide scalable I/O performance and reaches millions of metadata operations already for a small number of nodes, significantly outperforming the capabilities of common parallel file systems., Peer Reviewed, Postprint (author's final draft)

POSIX is a standard for operating systems, with a substantial part devoted to specifying file-system operations. File-system operations exhibit complex concurrent behaviour, comprising multiple actions affecting different parts of the state: typically, multiple atomic reads followed by an atomic update. However, the standard's description of concurrent behaviour is unsatisfactory: it is fragmented; contains ambiguities; and is generally under-specified. We provide a formal concurrent specification of POSIX file systems and demonstrate scalable reasoning for clients. Our specification is based on a concurrent specification language, which uses a modern concurrent separation logic for reasoning about abstract atomic operations, and an associated refinement calculus. Our reasoning about clients highlights an important difference between reasoning about modules built over a heap, where the interference on the shared state is restricted to the operations of the module, and modules built over a file system, where the interference cannot be restricted as the file system is a public namespace. We introduce specifications conditional on context invariants used to restrict the interference, and apply our reasoning to the example of lock files.

Scheduling of processes is the basic task for a grid computing. This role is responsible for the allocation of time for computational agents. The calculation agent can include a wide range of devices, based on various types of computer systems. Is it possible to efficiently build a grid infrastructure in the company environment. The grid can be used in scientific and technical computing, as well as better load distribution of the individual computing systems and services. The scheduler is a major component of grid computing. The main task is to effectively distribute the load of the system and allocate tasks to places that are not sufficiently utilized at a given moment. The article also focuses on the relation between conflicting parameters, which relate to the quality of the planning process. Time calculation of the optimization algorithm affects the quality of the draft plan. It has a direct impact on the total period of the job processing. In the strategy of the scheduling there is a point where extensions of time have no effect on quality of the draft of the plan but getting worse the overall runtime of the job. The aim was to compare the common metaheuristic algorithms. From the measured values to propose a methodology for determining the optimum time for planning process. © Springer International Publishing Switzerland 2016.

Scheduling of processes is the basic task for a grid computing. This role is responsible for the allocation of time for computational agents. The calculation agent can include a wide range of devices, based on various types of computer systems. Is it possible to efficiently build a grid infrastructure in the company environment. The grid can be used in scientific and technical computing, as well as better load distribution of the individual computing systems and services. The scheduler is a major component of grid computing. The main task is to effectively distribute the load of the system and allocate tasks to places that are not sufficiently utilized at a given moment. The article also focuses on the relation between conflicting parameters, which relate to the quality of the planning process. Time calculation of the optimization algorithm affects the quality of the draft plan. It has a direct impact on the total period of the job processing. In the strategy of the scheduling there is a point where extensions of time have no effect on quality of the draft of the plan but getting worse the overall runtime of the job. The aim was to compare the common metaheuristic algorithms. From the measured values to propose a methodology for determining the optimum time for planning process. © Springer International Publishing Switzerland 2016.

The main purpose of this work is to explain the management and distribution of tasks in a grid middleware. The aim is to propose an environment that enables designing the batch jobs that use the standard software and system resources for communication and data exchange. The article explains JSDL specification for defining and management of one batch jobs. The motivation is to design a tool for an easy job definition. The result is a tool that does not require special programming objects for solving a specific task. This work deals with the mechanisms for monitoring and gathering information about the result of each processing task. The JSDL definitions provide the mechanism for the solution of these problems. Grid Scheduler more easily recognizes the status of a specific task. © Springer International Publishing Switzerland 2015.

El estándar POSIX provee una API para la comunicación y la sincronización entre procesos concurrentes, entre otros servicios, que resulte portable para diferentes sistemas operativos. Como toda interfaz general, POSIX brinda soporte a una gran cantidad de casos especiales, con mucho nivel de detalle, ofreciendo una granularidad elevada a la hora de enfrentar las posibles alternativas de programación que se pueden dar en una situación realista. Este grado de detalle, sin embargo, hace que la curva de aprendizaje de la API sea muy empinada. Por este motivo se ha creado una interfaz reducida, que sin traicionar los principios de la orginal, simplifica el acceso a las características fundamentales para los fines de la docencia de la asignatura de Informática Industrial. Aquí se presente un tutorial de las principales caracterísitas de esta API de POSIX reducida., Ingeniería de Sistemas y Automática

El estándar POSIX provee una API para la comunicación y la sincronización entre procesos concurrentes, entre otros servicios, que resulte portable para diferentes sistemas operativos. Como toda interfaz general, POSIX brinda soporte a una gran cantidad de casos especiales, con mucho nivel de detalle, ofreciendo una granularidad elevada a la hora de enfrentar las posibles alternativas de programación que se pueden dar en una situación realista. Este grado de detalle, sin embargo, hace que la curva de aprendizaje de la API sea muy empinada. Por este motivo se ha creado una interfaz reducida, que sin traicionar los principios de la orginal, simplifica el acceso a las características fundamentales para los fines de la docencia de la asignatura de Informática Industrial. Aquí se presente un tutorial de las principales caracterísitas de esta API de POSIX reducida., Ingeniería de Sistemas y Automática

El estándar POSIX provee una API para la comunicación y la sincronización entre procesos concurrentes, entre otros servicios, que resulte portable para diferentes sistemas operativos. Como toda interfaz general, POSIX brinda soporte a una gran cantidad de casos especiales, con mucho nivel de detalle, ofreciendo una granularidad elevada a la hora de enfrentar las posibles alternativas de programación que se pueden dar en una situación realista. Este grado de detalle, sin embargo, hace que la curva de aprendizaje de la API sea muy empinada. Por este motivo se ha creado una interfaz reducida, que sin traicionar los principios de la orginal, simplifica el acceso a las características fundamentales para los fines de la docencia de la asignatura de Informática Industrial. Aquí se presente un tutorial de las principales caracterísitas de esta API de POSIX reducida., Ingeniería de Sistemas y Automática

"Cryogenic: Enabling Power-Aware Applications on Linux" Desenvolupament d'un modul de Linux que permet reduir el consum d'energia en dispositius hardware a traves de cooperació entre aplicacions.

El estándar POSIX provee una API para la comunicación y la sincronización entre procesos concurrentes, entre otros servicios, que resulte portable para diferentes sistemas operativos. Como toda interfaz general, POSIX brinda soporte a una gran cantidad de casos especiales, con mucho nivel de detalle, ofreciendo una granularidad elevada a la hora de enfrentar las posibles alternativas de programación que se pueden dar en una situación realista. Este grado de detalle, sin embargo, hace que la curva de aprendizaje de la API sea muy empinada. Por este motivo se ha creado una interfaz reducida, que sin traicionar los principios de la orginal, simplifica el acceso a las características fundamentales para los fines de la docencia de la asignatura de Informática Industrial. Aquí se presente un tutorial de las principales caracterísitas de esta API de POSIX reducida., Ingeniería de Sistemas y Automática

L'objectiu del projecte és el disseny i implementació d'un computador al voltant d'un processador MIPS. Aquest computador ha de funcionar a una placa de demostració Terasic DE2-115, que disposa d'una FPGA Altera Cyclone IV.

Detta examensarbete behandlar problemet med att testa inbyggda system i kontorsmiljö. För att göra detta och därigenom kunna göra anrop på det inbyggda systemets API, måste detta anrop skickas som ett seriellt datapaket över en seriell kommunikationslänk som TCP/IP. Detta möjliggjordes genom att först upprätta en kommunikationslänk med protokollet TCP/IP, där användningen av POSIX-sockets tillämpades. För att packa ner och packa upp funktionsanropen till seriell data implementerades ett protokoll som följdes när detta utfördes. Hantering av data i samband med överföring över TCP/IP sköttes av ett protokoll vid namn BGSFP, ett protokoll som bygger på det tidigare protokollet TSFP.

Detta examensarbete behandlar problemet med att testa inbyggda system i kontorsmiljö. För att göra detta och därigenom kunna göra anrop på det inbyggda systemets API, måste detta anrop skickas som ett seriellt datapaket över en seriell kommunikationslänk som TCP/IP. Detta möjliggjordes genom att först upprätta en kommunikationslänk med protokollet TCP/IP, där användningen av POSIX-sockets tillämpades. För att packa ner och packa upp funktionsanropen till seriell data implementerades ett protokoll som följdes när detta utfördes. Hantering av data i samband med överföring över TCP/IP sköttes av ett protokoll vid namn BGSFP, ett protokoll som bygger på det tidigare protokollet TSFP.

With the rise of multi-core chips in commodity hardware, the need for specialized workloads to evaluate the performance of multi-core systems has become apparent. The current generation of workloads used for evaluating multi-core systems often consist of sequential programs not capable of running on multiple processors and are therefore of limited use for evaluating multi-core hardware. Such sequential programs fail to show the bene?ts of adding additional cores to a system, since the programs are not capable of using all of the available resources concurrently. Apple Inc. requested the development of a workload suite that would clearly show the bene?ts of increasing the number of cores, while stressing the main parts of the system. Key requirements for the workload are: Scalability, Reproducibility and Veri?ability. In this thesis report, we present the whole process of workload development for multi-core systems, starting from selecting the programs to be included in the workload, till the application of the workload to actual hardware. In addition, this report discusses the classi?cation of different programs based on fundamental algorithm classes called Dwarfs, which is the basis for selecting possible workload components. The thesis also presents the relevant technologies used for the parallelization of selected workload components. Finally, a case study is discussed showing how to use the developed workload in practice., Microelectronics & Computer Engineering, Electrical Engineering, Mathematics and Computer Science

El estudio de las llamadas al sistema POSIX es una materia habitual en el programa de muchas asignaturas relacionadas con los Sistemas Operativos. Dentro de estas, las llamadas relacionadas con la creación y gestión de procesos (fork, exec, wait, exit) suelen ser, por su propia naturaleza, difíciles de entender para el estudiante. Teniendo en cuenta este problema se ha desarrollado un sistema que visualiza gráficamente el comportamiento de estas llamadas a partir de la ejecución de un programa que las utilice. Dicho sistema facilita tanto al profesor la explicación de esta materia y como al alumno su comprensión. En este trabajo se describe dicho sistema., Peer Reviewed

With the rise of multi-core chips in commodity hardware, the need for specialized workloads to evaluate the performance of multi-core systems has become apparent. The current generation of workloads used for evaluating multi-core systems often consist of sequential programs not capable of running on multiple processors and are therefore of limited use for evaluating multi-core hardware. Such sequential programs fail to show the bene?ts of adding additional cores to a system, since the programs are not capable of using all of the available resources concurrently. Apple Inc. requested the development of a workload suite that would clearly show the bene?ts of increasing the number of cores, while stressing the main parts of the system. Key requirements for the workload are: Scalability, Reproducibility and Veri?ability. In this thesis report, we present the whole process of workload development for multi-core systems, starting from selecting the programs to be included in the workload, till the application of the workload to actual hardware. In addition, this report discusses the classi?cation of different programs based on fundamental algorithm classes called Dwarfs, which is the basis for selecting possible workload components. The thesis also presents the relevant technologies used for the parallelization of selected workload components. Finally, a case study is discussed showing how to use the developed workload in practice., Microelectronics & Computer Engineering, Electrical Engineering, Mathematics and Computer Science

Conceptes, solucions i implementació

Después de más de 25 años de intensa investigación, la planificación de sistemas de tiempo-real ha mostrado una transición que va desde una infraestructura basada en ejecutivos cíclicos, a modelos de planificación más flexibles, tales como planificación basada en prioridades estáticas y dinámicas, planificación de tareas no críticas, y planificación con retroalimentación, por nombrar algunas. A pesar de lo anterior, actualmente tan sólo unas cuantas políticas de planificación están disponibles para la implementación de sistemas de tiempo-real. Por ejemplo, la mayoría de los sistemas operativos de tiempo-real existentes proporcionan únicamente planificación basada en prioridades fijas. Sin embargo, no todos los requerimientos de las aplicaciones de tiempo-real pueden ser satisfactoriamente atendidos utilizando exclusivamente planificación estática. Existen sistemas constituidos por tareas críticas y no críticas que son planificados de mejor manera utilizando planificación basada en prioridades dinámicas. Además, se ha demostrado que la planificación dinámica permite una mayor utilización de los recursos del sistema. En años recientes, algunos autores han publicado diferentes esquemas para integrar nuevas políticas de planificación a un sistema operativo. Algunos de ellos proponen que los nuevos servicios de planificación se implementen a nivel de usuario, evitando así que la estructura interna del sistema operativo tenga que ser modificada, y ofreciendo la oportunidad de implementar y probar muchos de los resultados generados por el trabajo de investigación en el área de planificación de sistemas de tiempo-real. De entre los trabajos relacionados publicados a la fecha, destaca el Modelo para la Planificación Definida por el Usuario, propuesto por Mario Aldea y Michael González-Harbour. El modelo presenta una Interfaz para Programas de Aplicación (API) que permite crear y utilizar planificadores a nivel de usuario de manera compatible con el modelo de planificación

Plantejament i resolució pas a pas, amb implementació POSIX, d'exercicis de concurrència fonamentats en un clàssic

Plantejament i resolució pas a pas, amb implementació POSIX, d'un problema clàssic de concurrència d'un nivell de dificultat elevat

Conceptes, solucions i implementació

Plantejament i resolució pas a pas, amb implementació POSIX, d'exercicis de concurrència fonamentats en un clàssic

Plantejament i resolució pas a pas, amb implementació POSIX, d'un problema clàssic de concurrència d'un nivell de dificultat elevat

Conceptes, solucions i implementació

Plantejament i resolució pas a pas, amb implementació POSIX, d'un problema clàssic de concurrència d'un nivell de dificultat elevat

Plantejament i resolució pas a pas, amb implementació POSIX, d'exercicis de concurrència fonamentats en un clàssic

Después de más de 25 años de intensa investigación, la planificación de sistemas de tiempo-real ha mostrado una transición que va desde una infraestructura basada en ejecutivos cíclicos, a modelos de planificación más flexibles, tales como planificación basada en prioridades estáticas y dinámicas, planificación de tareas no críticas, y planificación con retroalimentación, por nombrar algunas. A pesar de lo anterior, actualmente tan sólo unas cuantas políticas de planificación están disponibles para la implementación de sistemas de tiempo-real. Por ejemplo, la mayoría de los sistemas operativos de tiempo-real existentes proporcionan únicamente planificación basada en prioridades fijas. Sin embargo, no todos los requerimientos de las aplicaciones de tiempo-real pueden ser satisfactoriamente atendidos utilizando exclusivamente planificación estática. Existen sistemas constituidos por tareas críticas y no críticas que son planificados de mejor manera utilizando planificación basada en prioridades dinámicas. Además, se ha demostrado que la planificación dinámica permite una mayor utilización de los recursos del sistema. En años recientes, algunos autores han publicado diferentes esquemas para integrar nuevas políticas de planificación a un sistema operativo. Algunos de ellos proponen que los nuevos servicios de planificación se implementen a nivel de usuario, evitando así que la estructura interna del sistema operativo tenga que ser modificada, y ofreciendo la oportunidad de implementar y probar muchos de los resultados generados por el trabajo de investigación en el área de planificación de sistemas de tiempo-real. De entre los trabajos relacionados publicados a la fecha, destaca el Modelo para la Planificación Definida por el Usuario, propuesto por Mario Aldea y Michael González-Harbour. El modelo presenta una Interfaz para Programas de Aplicación (API) que permite crear y utilizar planificadores a nivel de usuario de manera compatible con el modelo de planificación

Conceptes, solucions i implementació

Plantejament i resolució pas a pas, amb implementació POSIX, d'exercicis de concurrència fonamentats en un clàssic

Plantejament i resolució pas a pas, amb implementació POSIX, d'un problema clàssic de concurrència d'un nivell de dificultat elevat

Bakalářská práce se zabývá návrhem třídy v jazyce C++, která umožní událostmi řízenou komunikaci s obvodem FTDI. Práce se dále zabývá návrhem testovací aplikace, která ověří funkčnost komunikace C++ třídy s obvodem FTDI pod operač-ním systémem Linux. V programové části jsou popsány postupy vlastní komunikace, testování, připojení a manipulace s integrovaným obvodem FTDI pomocí spuštěného programu pod operačním systémem Linux., This bachelor thesis is about design and implementation of library for event-driven communication with the FTDI chip under Linux operating system. Implemen-tation is in C++ language. There is a test application to demonstrate connection and communication with FTDI chip trough the library., Katedra informačních technologií, Dokončená práce s úspěšnou obhajobou

Expressing a large number of lightweight, parallel threads in a shared address space significantly eases the task of writing a parallel program. Threads can be dynamically created to execute individual parallel tasks; the implementation schedules these threads onto the processors and effectively balances the load. However, unless the threads scheduler is designed carefully, such a parallel program may suffer poor space and time performance. Th this paper, we evaluate the performance of a native, lightweight POSIX threads (Pthreads) library on a shared memory machine using a set of parallel benchmarks that dynamically create a large number of threads. By studying the performance of one of the benchmarks, matrix multiply, we show how simple, yet provably good modifications to the library can result in significantly improved space and time performance. With the modified Pthreads library, each of the parallel benchmarks performs as well as its coarse-grained, hand-partitioned counterpart. These results demonstrate that, provided we use a good scheduler, the rich functionality and standard API of Pthreads can be combined with the advantages of dynamic, lightweight threads to result in high performance.

Grand Central Dispatch je systém, ktorý aplikáciám umožňuje optimálne využitie viacjadrových zariadení od firmy Apple. Tento systém je veľkou časťou podporovaný operačným systémom Apple platforiem. Cieľom tejto bakalárskej práce bolo analyzovať systém a následne navrhnúť a implementovať obdobu v podobe knižnice v jazyku C++. Táto knižnica poskytuje rozhranie a funkcionalitu podobnú existujúcemu systému., Grand Central Dispatch is a system which allows applications to optimally use multi-core Apple devices. This system is for the most part supported by operating systems of Apple platforms. The goal of this bachelor's thesis was to analyze the system and subsequently design and implement a library in C++. This library provides interface and functionality similar to the existing system.

Tato práce se zabývá problematikou přenosu trojrozměrných dat po síti a jejich následným vykreslením. Důraz je kladen na efektivitu přenosu, což je zajištěno implementací vlastního komunikačního protokolu fungujícího nad protokolem UDP a adaptací technologie statického Level of Detail pro potřeby přenosu. Pro vykreslení přenesené geometrie je navrhnut triviální grafický engine. Závěrem jsou prezentovány testy efektivity výsledného protokolu., This thesis is oriented on problematics of streaming 3D geometrics over network. Main importance is seen in efectivity of streaming, for what there is presented special protocol, working over protocol UDP, and adaptation of Level of Detail. For visualization of transmitted geometry trivial graphical engine is developed. In the end there are presented results of tests, oriented on protocol's efectivness.

Grand Central Dispatch je systém, ktorý aplikáciám umožňuje optimálne využitie viacjadrových zariadení od firmy Apple. Tento systém je veľkou časťou podporovaný operačným systémom Apple platforiem. Cieľom tejto bakalárskej práce bolo analyzovať systém a následne navrhnúť a implementovať obdobu v podobe knižnice v jazyku C++. Táto knižnica poskytuje rozhranie a funkcionalitu podobnú existujúcemu systému., Grand Central Dispatch is a system which allows applications to optimally use multi-core Apple devices. This system is for the most part supported by operating systems of Apple platforms. The goal of this bachelor's thesis was to analyze the system and subsequently design and implement a library in C++. This library provides interface and functionality similar to the existing system.

Práce se zabývá vytvořením systému, který by detekoval průjezd vlakového vagónu a očísloval jej dle Mezinárodní železniční unie. Na začátku práce jsou rozebrány využité metody pro správnou detekci průjezdu kola včetně časového záznamu. Také uvádím typy senzorů s jejich vlastnostmi vzhledem k využití na železnici. Rozebírám význam jednotlivých cifer v číslování dle UIC. Vytvářím návrh systému, uvádím jeho zapojení a vztahy mezi jednotlivými podsystémy. Kladu důraz na takové řešení, aby záznam o kole byl za každých okolností včasný a co nejvíce přesný. Využívám k tomu systém pracující v reálném čase. Dále verifikuji samotný měřící program, abych zajistil celkovou bezchybnost měřícího prvku systému. V následující části popisuji prototyp programu, který zpracovává data z měření. Rozepisuji algoritmy, které jsem využil pro detekci kol a následně vlakových vagónů. V navazující kapitole uvádím způsob práce s externí kamerou pro detekci čísla dle UIC. V posledních kapitolách popisuji testovací prostředí, ve kterých dané řešení bylo otestováno, a shrnuji výsledky testů na reálné vlakové trati., The diploma thesis deals with design and development of the system which detects and numbers train carriages in compliance with International Union of Railways. Firstly, methods for correct detection of passing wheel including time records are analysed. Also, the summary of detection sensors used in railway industry is referred. I analyse meaning of each digit in numbering according to the UIC. The system solution is designed and the interaction and communication with other sub-systems is discussed. I put emphasis on the kind of solution that returns as accurate record as possible under any circumstances. The system operates in real time. Further, the results of measuring program are back-tested in order to verify low-deviation of measuring system component. The following section describes program prototype, which processes the recorded data. The algorithms which I used for the detection of wheel and train carriages are described. In the following chapter I discuss the usage of an external camera detecting the numbers in accordance to the UIC. In the last chapter, I describe the test environment in which the solution has been tested, and summarize the results of tests on a real life railway.

Tato práce se zabývá problematikou přenosu trojrozměrných dat po síti a jejich následným vykreslením. Důraz je kladen na efektivitu přenosu, což je zajištěno implementací vlastního komunikačního protokolu fungujícího nad protokolem UDP a adaptací technologie statického Level of Detail pro potřeby přenosu. Pro vykreslení přenesené geometrie je navrhnut triviální grafický engine. Závěrem jsou prezentovány testy efektivity výsledného protokolu., This thesis is oriented on problematics of streaming 3D geometrics over network. Main importance is seen in efectivity of streaming, for what there is presented special protocol, working over protocol UDP, and adaptation of Level of Detail. For visualization of transmitted geometry trivial graphical engine is developed. In the end there are presented results of tests, oriented on protocol's efectivness.

Práce se zabývá vytvořením systému, který by detekoval průjezd vlakového vagónu a očísloval jej dle Mezinárodní železniční unie. Na začátku práce jsou rozebrány využité metody pro správnou detekci průjezdu kola včetně časového záznamu. Také uvádím typy senzorů s jejich vlastnostmi vzhledem k využití na železnici. Rozebírám význam jednotlivých cifer v číslování dle UIC. Vytvářím návrh systému, uvádím jeho zapojení a vztahy mezi jednotlivými podsystémy. Kladu důraz na takové řešení, aby záznam o kole byl za každých okolností včasný a co nejvíce přesný. Využívám k tomu systém pracující v reálném čase. Dále verifikuji samotný měřící program, abych zajistil celkovou bezchybnost měřícího prvku systému. V následující části popisuji prototyp programu, který zpracovává data z měření. Rozepisuji algoritmy, které jsem využil pro detekci kol a následně vlakových vagónů. V navazující kapitole uvádím způsob práce s externí kamerou pro detekci čísla dle UIC. V posledních kapitolách popisuji testovací prostředí, ve kterých dané řešení bylo otestováno, a shrnuji výsledky testů na reálné vlakové trati., The diploma thesis deals with design and development of the system which detects and numbers train carriages in compliance with International Union of Railways. Firstly, methods for correct detection of passing wheel including time records are analysed. Also, the summary of detection sensors used in railway industry is referred. I analyse meaning of each digit in numbering according to the UIC. The system solution is designed and the interaction and communication with other sub-systems is discussed. I put emphasis on the kind of solution that returns as accurate record as possible under any circumstances. The system operates in real time. Further, the results of measuring program are back-tested in order to verify low-deviation of measuring system component. The following section describes program prototype, which processes the recorded data. The algorithms which I used for the detection of wheel and train carriages are described. In the following chapter I discuss the usage of an external camera detecting the numbers in accordance to the UIC. In the last chapter, I describe the test environment in which the solution has been tested, and summarize the results of tests on a real life railway.

Grand Central Dispatch je systém, ktorý aplikáciám umožňuje optimálne využitie viacjadrových zariadení od firmy Apple. Tento systém je veľkou časťou podporovaný operačným systémom Apple platforiem. Cieľom tejto bakalárskej práce bolo analyzovať systém a následne navrhnúť a implementovať obdobu v podobe knižnice v jazyku C++. Táto knižnica poskytuje rozhranie a funkcionalitu podobnú existujúcemu systému., Grand Central Dispatch is a system which allows applications to optimally use multi-core Apple devices. This system is for the most part supported by operating systems of Apple platforms. The goal of this bachelor's thesis was to analyze the system and subsequently design and implement a library in C++. This library provides interface and functionality similar to the existing system.

Grand Central Dispatch je systém, ktorý aplikáciám umožňuje optimálne využitie viacjadrových zariadení od firmy Apple. Tento systém je veľkou časťou podporovaný operačným systémom Apple platforiem. Cieľom tejto bakalárskej práce bolo analyzovať systém a následne navrhnúť a implementovať obdobu v podobe knižnice v jazyku C++. Táto knižnica poskytuje rozhranie a funkcionalitu podobnú existujúcemu systému., Grand Central Dispatch is a system which allows applications to optimally use multi-core Apple devices. This system is for the most part supported by operating systems of Apple platforms. The goal of this bachelor's thesis was to analyze the system and subsequently design and implement a library in C++. This library provides interface and functionality similar to the existing system.

Tato práce se zabývá problematikou přenosu trojrozměrných dat po síti a jejich následným vykreslením. Důraz je kladen na efektivitu přenosu, což je zajištěno implementací vlastního komunikačního protokolu fungujícího nad protokolem UDP a adaptací technologie statického Level of Detail pro potřeby přenosu. Pro vykreslení přenesené geometrie je navrhnut triviální grafický engine. Závěrem jsou prezentovány testy efektivity výsledného protokolu., This thesis is oriented on problematics of streaming 3D geometrics over network. Main importance is seen in efectivity of streaming, for what there is presented special protocol, working over protocol UDP, and adaptation of Level of Detail. For visualization of transmitted geometry trivial graphical engine is developed. In the end there are presented results of tests, oriented on protocol's efectivness.

Práce se zabývá vytvořením systému, který by detekoval průjezd vlakového vagónu a očísloval jej dle Mezinárodní železniční unie. Na začátku práce jsou rozebrány využité metody pro správnou detekci průjezdu kola včetně časového záznamu. Také uvádím typy senzorů s jejich vlastnostmi vzhledem k využití na železnici. Rozebírám význam jednotlivých cifer v číslování dle UIC. Vytvářím návrh systému, uvádím jeho zapojení a vztahy mezi jednotlivými podsystémy. Kladu důraz na takové řešení, aby záznam o kole byl za každých okolností včasný a co nejvíce přesný. Využívám k tomu systém pracující v reálném čase. Dále verifikuji samotný měřící program, abych zajistil celkovou bezchybnost měřícího prvku systému. V následující části popisuji prototyp programu, který zpracovává data z měření. Rozepisuji algoritmy, které jsem využil pro detekci kol a následně vlakových vagónů. V navazující kapitole uvádím způsob práce s externí kamerou pro detekci čísla dle UIC. V posledních kapitolách popisuji testovací prostředí, ve kterých dané řešení bylo otestováno, a shrnuji výsledky testů na reálné vlakové trati., The diploma thesis deals with design and development of the system which detects and numbers train carriages in compliance with International Union of Railways. Firstly, methods for correct detection of passing wheel including time records are analysed. Also, the summary of detection sensors used in railway industry is referred. I analyse meaning of each digit in numbering according to the UIC. The system solution is designed and the interaction and communication with other sub-systems is discussed. I put emphasis on the kind of solution that returns as accurate record as possible under any circumstances. The system operates in real time. Further, the results of measuring program are back-tested in order to verify low-deviation of measuring system component. The following section describes program prototype, which processes the recorded data. The algorithms which I used for the detection of wheel and train carriages are described. In the following chapter I discuss the usage of an external camera detecting the numbers in accordance to the UIC. In the last chapter, I describe the test environment in which the solution has been tested, and summarize the results of tests on a real life railway.