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The DARTWARS project has the goal of developing high-performing innovative traveling wave parametric amplifiers with high gain, large bandwidth, high saturation power, and nearly quantum-limited noise. The target frequency region for its applications is 5–10 GHz, where the expected noise temperature is below 600 mK. The development follows two different approaches, one based on Josephson junctions and one based on kinetic inductance of superconductors. This contribution mainly focuses on the Josephson traveling wave parametric amplifier, presenting its design, preliminary measurements and the test of homogeneity of arrays of Josephson junctions.

This paper presents a flying capacitor linear amplifier (FCLA) without p-channel MOSFETs. The FCLA is an advanced topology for the conventional class-B linear amplifier to enhance the conversion efficiency. It maintains multiple voltages by flying capacitors in the circuit and reduces the linear operation losses generated in the MOSFETs as the number of the series connected MOSFETs increases. As the result, the FCLA with a high number of series devices can achieve a noiseless and no-harmonic output voltage maintaining high efficiency. The conventional FCLA typically utilizes complementary operation between n-channel and p-channel MOSFETs. However, p-channel MOSFETs have worse characteristics than those of n-channel MOSFETs in general. It causes a limitation of the efficiency improvement of the whole circuit. In particular, when the number of series devices increases, the total series on-state resistance of the current path increases more by that of the p-channel MOSFETs. Therefore, it is desirable to use only n-channel MOSFETs for all the power devices. In this study, a circuit configuration of the FCLA using individual linear gate circuits for each MOSFET. It does not only achieve capacitor voltage balance, but also makes it possible to use only n-channel MOSFETs. It is verified that the proposed circuit configuration with only using n-channel MOSFETs realizes higher efficiency than that of the conventional FCLA.

The Wavelength-shifting Optical Module (WOM) is a novel photosensor concept for the instrumentation of large detector volumes with single-photon sensitivity. The key objective is to improve the signal-to-noise ratio, which is achieved by decoupling the photosensitive area of a sensor from the cathode area of its photomultiplier tube (PMT). The WOM consists of a transparent tube with two PMTs attached to its ends. The tube is coated with wavelength-shifting paint that absorbs ultraviolet photons with nearly 100% efficiency. Depending on the environment, e.g., air (ice), up to 73% (41%) of the subsequently emitted optical photons can be captured by total internal reflection and propagate towards the PMTs, where they are recorded. The optical properties of the paint, the geometry of the tube, and the coupling of the tube to the PMTs have been optimized for maximal sensitivity based on theoretical derivations and experimental evaluations. Prototypes were built to demonstrate the technique and to develop a reproducible construction process. Important measurable characteristics of the WOM are the wavelength-dependent effective area, the transit time spread of detected photons, and the signal-to-noise ratio. The WOM outperforms bare PMTs, especially with respect to the low signal-to-noise ratio with an increase of a factor up to 8.9 in air (5.2 in ice). Since the gain in sensitivity is mostly in the UV regime, the WOM is an ideal sensor for Cherenkov and scintillation detectors., Peer Reviewed

This article presents the experimentally characterized performance of a low noise and wideband sensor readout integrated circuit (ROIC). The ROIC is designed to detect small amounts of charge generated by a silicon p-i-n detector as a result of particle detection, with very high time resolution and limited power consumption. The architecture of the ROIC permits the analog components of the particle readout to be designed with a reduced bandwidth by implementing the so-called intersymbol interference (ISI) cancellation technique, which improves the noise performance, while reducing the deterministic ISI-induced errors associated with the narrowband circuit; hence, a low error rate (ER) can be maintained. The readout is designed to detect 160 aC charge portions delivered randomly by the detector at a maximum of 4 × 108 events/s with a small average ER while consuming 2.85 mW. Detailed information about the ROIC designed in 65-nm CMOS technology, and the simulated performance, are already reported in a previous publication. This article aims to present the challenges related to the design of the test setup and the obtained experimental results with the first prototype of the ROIC, as well as to discuss the data acquisition process., Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., Electronic Instrumentation

This paper presents a flying capacitor linear amplifier (FCLA) without p-channel MOSFETs. The FCLA is an advanced topology for the conventional class-B linear amplifier to enhance the conversion efficiency. It maintains multiple voltages by flying capacitors in the circuit and reduces the linear operation losses generated in the MOSFETs as the number of the series connected MOSFETs increases. As the result, the FCLA with a high number of series devices can achieve a noiseless and no-harmonic output voltage maintaining high efficiency. The conventional FCLA typically utilizes complementary operation between n-channel and p-channel MOSFETs. However, p-channel MOSFETs have worse characteristics than those of n-channel MOSFETs in general. It causes a limitation of the efficiency improvement of the whole circuit. In particular, when the number of series devices increases, the total series on-state resistance of the current path increases more by that of the p-channel MOSFETs. Therefore, it is desirable to use only n-channel MOSFETs for all the power devices. In this study, a circuit configuration of the FCLA using individual linear gate circuits for each MOSFET. It does not only achieve capacitor voltage balance, but also makes it possible to use only n-channel MOSFETs. It is verified that the proposed circuit configuration with only using n-channel MOSFETs realizes higher efficiency than that of the conventional FCLA.

The recording of neural signals with small monolithically integrated amplifiers is of high interest in research as well as in commercial applications, where it is common to acquire 100 or more channels in parallel. This paper reviews the recent developments in low-noise biomedical amplifier design based on CMOS technology, including lateral bipolar devices. Seven major circuit topology categories are identified and analyzed on a per-channel basis in terms of their noise-efficiency factor (NEF), input-referred absolute noise, current consumption, and area. A historical trend towards lower NEF is observed whilst absolute noise power and current consumption exhibit a widespread over more than five orders of magnitude. The performance of lateral bipolar transistors as amplifier input devices is examined by transistor-level simulations and measurements from five different prototype designs fabricated in 180 nm and 350 nm CMOS technology. The lowest measured noise floor is 9.9 nV/√ Hz with a 10 µA bias current, which results in a NEF of 1.2.

The purpose of this thesis is to evaluate a top-level topology for ultra-accurate power supplies. Chapter 3 shows that precision power supplies exist, but these are expensive and not stable on the long term. The correction scheme proposed in chapter 2 brings the accuracy of the best metrology systems to a high efficiency, low-noise power sup-ply at a lower cost than either the multimeter capable of such accuracyor the power supply capable of such low noise.Whether this is possible hinges on the orthagonality of the top-level design. Separation of functionality should allow each component to have fewer or even only one selection criterium to perform its function. This greatly reduces the cost and design complexity. To verify the theory behind top-level design, the critical parts are designed with available components and tested. This should reveal any practical limitations which may render the approach useless in a realistic scenario., Electrical Engineering | Microelectronics

The purpose of this thesis is to evaluate a top-level topology for ultra-accurate power supplies. Chapter 3 shows that precision power supplies exist, but these are expensive and not stable on the long term. The correction scheme proposed in chapter 2 brings the accuracy of the best metrology systems to a high efficiency, low-noise power sup-ply at a lower cost than either the multimeter capable of such accuracyor the power supply capable of such low noise.Whether this is possible hinges on the orthagonality of the top-level design. Separation of functionality should allow each component to have fewer or even only one selection criterium to perform its function. This greatly reduces the cost and design complexity. To verify the theory behind top-level design, the critical parts are designed with available components and tested. This should reveal any practical limitations which may render the approach useless in a realistic scenario., Electrical Engineering | Microelectronics

This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal recording. Among other features, it uses a subthreshold source-follower biquad in the forward path to reduce noise and avoid the implementation of a ripple rejection loop. The prototype was designed in 0.18μm CMOS technology with a 1V supply. Post-layout simulations were carried out showing a power consumption below 2μW and an integrated input-referred noise of 0.75μV rms , with a noise floor below 50 nV√Hz, over a bandwidth from 1 to 200Hz, for a noise efficiency factor of 2.7.

With the advent of the Internet of things, wearable sensing devices are gaining importance in our daily lives for applications like vital signal monitoring during sport and health diagnostics. Amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) fabricated on flexible large-area substrates are a very interesting platform to build wearable sensing devices due to their flexibility, conformability to the human body, and low cost. For this paper four different bio-signal sensing front-end circuits based on a-IGZO TFTs are designed, fabricated, measured and compared, focusing on three performance indicators which are in a trade-off: power efficiency factor (PEF), area occupation and input impedance. Considering a 200 Hz bandwidth, the measured PEF varies between 4.7 × 105 and 7.5 × 106. The area occupation spans from 4.2 to 37 mm2, while the input impedance at 1 Hz varies from 5.3 to 55.3 MΩ. The front-ends based on diode-load amplifiers are compact but have the lowest input impedance and need external capacitors; a front-end exploiting positive feedback impedance boosting has the highest input impedance and is fully integrated on foil, but occupies the largest area.

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models., Electronic Instrumentation

There is high demand for research into the innovation and development of miniaturized electronics devices for biomedical applications such as implantable medical devices (IMD), neural prostheses (NP), embedded neural systems, body area network (BAN) systems and wireless biosensors systems (WBS) for the monitoring, treatment and diagnostics of diseases such as retinal degenerative diseases (bionic eye), hearing loss (bionic ear), and epilepsy (neurobionics). These electronic systems must be wireless as wires penetrating through human skin increase the risk of infections as they act as conduits for viruses and bacteria and they also limit the flexibility of movement for patients. It is critical to have the smallest size possible for implanted devices to minimize required space, and to have high quality implant grades and off-chip components. Therefore, an integrated design for transceivers in single chips without any cheap components is preferable. Another advantage of minimum size and integrated transceiver design in a single chip is that it minimizes power consumption and heating. Ultra-low power transceivers are essential because implanted batteries are undesirable due to their limited lifespan and the risk of infection they pose. Also, a limited amount of power can be transferred through the wireless power link system, and in the bionic eye, most of the transferred power will be consumed for stimulation in the electrodes array. Frequency is another important factor and limitation of transceiver designs in biomedical applications. The Medical Implant Communication Service (MICS) frequency band (402-405 MHz) is a relatively low frequency and has a small channel bandwidth. Therefore, achieving an ultra-low power design of less than one milliwatt remains challenging. There is a high amount of data transmitted and received in some implantable biomedical devices like retinal prostheses (bionic eyes) so high-speed transceiver systems are required for these applications.

This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS) image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS) technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models., Electronic Instrumentation

Faithful recording of the biopotential signal is the prerequisite for the diagonosis and treatment of various diseases. The instrumentation amplfier is the key block in such a biopotential recording system. It is required to have a large input impedance, high gain, high CMRR, and low noise. The chopper capacitivley-coupled instrumentation amplifier (CCIA) is a popular candidate due to its good noise efficiency. To handle the electrode offset (EOS) induced by the electrode-tissue interface, a DC-servo loop (DSL) is added. However, there is a tradeoff between the noise performance and the EOS handling range, which is the main focus of this paper. The measurement result shows that supplied by 1.2V and consuming 2.9µA, the chopper CCIA achieves a noise spectrum of 47nV/√Hz and is capable of handling EOS of ±50mV.

Faithful recording of the biopotential signal is the prerequisite for the diagonosis and treatment of various diseases. The instrumentation amplfier is the key block in such a biopotential recording system. It is required to have a large input impedance, high gain, high CMRR, and low noise. The chopper capacitivley-coupled instrumentation amplifier (CCIA) is a popular candidate due to its good noise efficiency. To handle the electrode offset (EOS) induced by the electrode-tissue interface, a DC-servo loop (DSL) is added. However, there is a tradeoff between the noise performance and the EOS handling range, which is the main focus of this paper. The measurement result shows that supplied by 1.2V and consuming 2.9µA, the chopper CCIA achieves a noise spectrum of 47nV/√Hz and is capable of handling EOS of ±50mV.

A deep subelectron temporal noise CMOS image sensor (CIS) with a Gm-cell based pixel and a correlated-double charge-domain sampling technique has been developed for photon-starved imaging applications. With the proposed technique, the CIS, which is implemented in a standard 0.18-μm CIS process, features pixel-level amplification and achieves an input-referred noise of 0.5 e−rms with a correlated double sampling period of 5μs and a row read-out time of 10 μs. The proposed structurealso realizes a variable conversion gain (CG) with a period-controlled method. This enables the read-out path CG and the noise-equivalent number of electrons to be programmable according to the application without any change in hardware. The experiments show that the measured CG can be tuned from 50 μV/e- to 1.6 mV/e- with a charging period from 100 ns to 4μs. The measured characteristics of the prototype CIS are in a good agreement with expectations, demonstrating the effectiveness of the proposed techniques., Accepted Author Manuscript, Electronic Instrumentation

Faithful recording of the biopotential signal is the prerequisite for the diagonosis and treatment of various diseases. The instrumentation amplfier is the key block in such a biopotential recording system. It is required to have a large input impedance, high gain, high CMRR, and low noise. The chopper capacitivley-coupled instrumentation amplifier (CCIA) is a popular candidate due to its good noise efficiency. To handle the electrode offset (EOS) induced by the electrode-tissue interface, a DC-servo loop (DSL) is added. However, there is a tradeoff between the noise performance and the EOS handling range, which is the main focus of this paper. The measurement result shows that supplied by 1.2V and consuming 2.9µA, the chopper CCIA achieves a noise spectrum of 47nV/√Hz and is capable of handling EOS of ±50mV.

In this report, we demonstrated a handheld wireless voltage-clamp amplifier for current measurement of nanopore sensors. This amplifier interfaces a sensing probe and connects wirelessly with a computer or smartphone for the required stimulus input, data processing and storage. To test the proposed Signal Transduction by Ion Nanogating (STING) wireless amplifier, in the current study the system was tested with a nano-pH sensor to measure pH of standard buffer solutions and the performance was compared against the commercial voltage-clamp amplifier. To our best knowledge, STING amplifier is the first miniaturized wireless voltage-clamp platform operated with a customized smart-phone application (app).

Pressing performance demands require next-generation biosensors to detect target chemical and biological molecules with higher sensitivity, shorter response times, and lower detection limit. Micro- and nanoscale devices are attractive for a wide range of biosensor applications since at small scale, in addition to being more compact, the device may exhibit improved performance. The benefits include minimization of tissue damage for implantable devices, improved spatial resolution and sensitivity, as well as increased surface charge to mass ratio, which is important for the performance of our novel technology for nucleic acid detection described below. Borrowing from the processing technologies used in the semiconductor industry, we implemented micromachining techniques to fabricate devices at both the micro- and nanoscale. In this dissertation, we present our work on the fabrication and characterization of two next-generation biosensors. The first device we fabricated is a sequence-specific nucleic acid sensor based on the blockage of a nanopore. Current methods for nucleic acid detection generally rely on polymerase chain reaction (PCR) and fluorescent labeling, however, these methods render the devices slow, expensive, complex, and bulky. In order to address these limitations, a new sensor was fabricated from a single glass wafer, consisting of a glass nanopore in a thin glass membrane. For nanopore sensing, low frequency noise is critical since it limits the discrimination of signal change based on target analyte movement from the fluctuation of noise. To further our understanding of nanopores, we observed how different pore geometries affect noise characteristics, and then compared this newly developed glass nanopore to conventional Si-based nanopores. Based on the analysis, low-noise glass nanopores, suitable for sequence-specific nucleic acid detection, were fabricated. By scaling down the pore diameter to the nano-regime, 1 aM detection of 16S rRNA from Escher

Noise in electronic circuits can sometimes cause problems. It is especially problematic in for example high sensitive sensors and high end audio and video equipment. In audio and video equipment the noise will make its way into the sound and picture reducing the overall quality. Sensors that are constructed to sense extremely small changes can only pick up changes larger than the noise floor of the circuit. By lowering the noise, sensors can achieve higher accuracy. This thesis presents an ultra low noise solution of the biasing circuitry to the bolometer used in one of FLIR Systems high end cameras. The bolometer uses different adjustable direct current voltage sources and is extremely sensitive to noise. The purpose is to improve the picture quality and the thermal measurement resolution. A prototype circuit was constructed and in the end of the thesis a final circuit with successful result will be presented.

Noise in electronic circuits can sometimes cause problems. It is especially problematic in for example high sensitive sensors and high end audio and video equipment. In audio and video equipment the noise will make its way into the sound and picture reducing the overall quality. Sensors that are constructed to sense extremely small changes can only pick up changes larger than the noise floor of the circuit. By lowering the noise, sensors can achieve higher accuracy. This thesis presents an ultra low noise solution of the biasing circuitry to the bolometer used in one of FLIR Systems high end cameras. The bolometer uses different adjustable direct current voltage sources and is extremely sensitive to noise. The purpose is to improve the picture quality and the thermal measurement resolution. A prototype circuit was constructed and in the end of the thesis a final circuit with successful result will be presented.

This thesis presents a low-power low-noise instrumentation amplifier designed to be implemented in 40 nm CMOS technology and operating from a 0.6 V supply, intended for use in electrocardiogram (ECG) and bio-impedance (BioZ) signal acquisition. This instrumentation amplifier has one ECG channel, one BioZ channel and allows both signals to be measured at the same time. The core of the system is an AC-coupled instrumentation amplifier. A DC servo-loop is applied to handle large differential electrode offset (>300 mV) and a positive feedback loop is used to boost the input impedance (>100 MΩ). This instrumentation amplifier achieves low noise (<1 μVrms over a bandwidth 150 Hz), large CMRR (>100 dB) while only consuming 1 μW power. The instrumentation amplifier has a noise efficiency factor (NEF) of 2.4 and it occupies only 0.1 mm2 chip area., Electrical Engineering, Mathematics and Computer Science, Microelectronics

Design and implementation of a novel ultra-low power (ULP) operationaltransconductance amplifier (OTA) meant for recording Electrocorticography signals ispresented in this thesis. The design of the amplifier is done in weak inversion (or subthreshold) region of operation of MOSFET and was fabricated in IBM 130 nm standardCMOS process. This thesis discusses the design and measurement challenges associatedwith analog/mixed signal design in this region of operation. The ULP closed loop fullydifferential OTA is designed for voltage gain of 40 dB for a frequency ranging from 15 Hz to270 Hz with input referred noise voltage less than 5 uVrms across bandwidth of operation.Total power dissipation for the novel complementary OTA structure designed in weakinversion region is measured to be 216 nW for a supply of 0.4 V.

Aiming for the application to the future spacecraft attitude control system, the high performance Fiber Optic Gyro Inertial Reference Unit (FOG-IRU) is being studied. To fulfill the requirements of low noise, stable bias and stable scale factor, adopted are the high power Fiber Light Source, a long fiber coil (several kilo-meters) and the digital serrodyne closed loop configuration. This paper outlines the result of FOG-IRU development during FY15 such as improvement of 1st FOG experimental model, radiation test of high power light source, design and manufacturing of 2nd FOG experimental models, implementation of light source noise compensation circuit and component system design of FOG-IRU., JAXA Research and Development Memorandum, 宇宙航空研究開発機構研究開発資料

Based on the results of the developed analytical theory, the authors propose to use the magnonic crystal patterned on the YIG magnetic film as an efficient delay line in the feedback loop of tunable auto-oscillator. This allows the reduction of the inhomogenity of bias magnetic field and the rasing of the power of input signal in virtue of decreasing the length and increasing the thickness of such delay line as compare to the YIG film with no pattern. In turn, use of this magnonic crystal opens a way to improve noise properties of the auto-oscillator.

In this paper, we propose a discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather than opamps, thus being compatible with digital nanoscale technology. In the voltage-sampling mode, the gm-cell is bypassed so the filter is fully passive. A 7th-order filter prototype operating at 800 MS/s sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth of this filter is programmable between 400 kHz to 30 MHz with 100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the averaged spot noise is 4.57 nV/$surd$ Hz. It consumes 2 mW at 1.2 V and occupies 0.42 mm 2., Microelectronics, Electrical Engineering, Mathematics and Computer Science

With the advent of Internet of Things (IoT) it has become clear that radio-frequency (RF) designers have to be aware of power constraints, e.g., in the design of simplistic ultra-low power receivers often used as wake-up radios (WuRs). The objective of this work, one of the first systematic studies of power bounds for RF-systems, is to provide an overview and intuitive feel for how power consumption and sensitivity relates for low-power receivers. This was done by setting up basic circuit schematics for different radio receiver architectures to find analytical expressions for their output signal-to-noise ratio including power consumption, bandwidth, sensitivity, and carrier frequency. The analytical expressions and optimizations of the circuits give us relations between dc-energy-per-bit and receiver sensitivity, which can be compared to recent published low-power receivers. The parameter set used in the analysis is meant to reflect typical values for an integrated 90 nm complementary metal-oxide-semiconductor fabrication processes, and typical small sized RF lumped components., Article number: 6866244

[ANGLÈS] This thesis report describes the design process, the implementation and the simulation and measurement results of two different readout circuits to be used with two monolithic MEMS accelerometers fabricated by post-CMOS surface micromachining based on isotropic wet etching in IHP SiGe 0,25 μm technology. The first design is used with a 50 fF z-axis sensor and the second design with a 200 fF sensor as well as the first sensor. The approach used has been the Continuous Time Voltage (CTV) sensing implemented in two ways. The first readout circuit implements a CTV sensing utilising an open-loop topology whereas the second design implements a CTV sensing with a closed-loop amplifier and low duty-cycle reset. In both designs, chopper stabilisation has been implemented to get rid of DC offset and Flicker noise, making both designs to work beyond the noise corner frequency to obtain the lowest achievable noise floor: thermal noise. The target during the design of both circuits has been to design amplifying circuits with a thermal noise equal or below the Brownian-noise of the capacitive sensor in order to make the noise from the sensor to be dominant. This has been possible by means of a deep study of noise and the optimisation of the transistor dimensions ratio that have the highest noise influence: input pair transistors. In both cases, equations that relate input node capacitance with noise have been found and final values have been obtained by fine tuning using the design software following the hypothesis found in the derived equations. The first design has been fabricated and total noise using opamp measured noise shows a noise floor of 238μg/rt-Hz, a lower noise value than designs with sensors having a similar sensitivity found in the literature. Second design has not been fabricated yet, but simulations also show a good noise performance of 20μg/rt-Hz with the second sensor. However, differences in measured and simulated noise in the first design shows that, [CASTELLÀ] Esta tesis describe el proceso de diseño, la implementación y los resultados de las simulaciones y las medidas de dos circuitos de acondicionamiento de señal para ser usados con dos sensores de aceleración monolíticos fabricados mediante el proceso post-CMOS surface micromachining basado en isotropic wet etching en tecnología IHP SiGe 0,25 μm. El primer diseño se ha implementado con un sensor de 50 fF de z-axis, mientras que el segundo se ha implementado, además de con éste mismo sensor, con un segondo sensor de 200 fF. El método utilizado ha sido el de sensado de Voltage en Tiempo Continuo (CTV) implementado de dos maneras. El primer diseño implementa el sensador CTV utilisando una topología en lazo abierto, mientras que el segundo diseño implementa el sensado CTV mediante un amplificador en lazo cerrado y un reset con bajo duty-cycle. En ambos diseños, se ha usado la estabilizació chopper para eliminar el offset DC y el ruido Flicker, haciendo trabajar ambos diseños por encima de la frecuencia codo de ruido para obtener el riudo mínimo: ruido térmico. El objetivo durante el diseño de los dos circuitos ha sido el de diseñar dos circuitos de acondicionamiento con un ruido térmico igual o inferior al ruido Browniano del sensor capacitivo de modo que el ruido dominante sea el que proveniente del sensor. Ésto ha sido posible gracias a un profundo estudio del ruido y la optimizacion de las dimensiones de los transistores que tienen una mayor influencia: el par de transistores de entrada. En los dos casos, se han elaborado equaciones que relacionan la capacidad en el nodo de entrada con el ruido, y los valores finalmente usados han sido obtenidos mediante el software de diseño siguiendo las hipótesis marcadas por las expresiones obtenidas. El primer diseño ha sigdo fabricado i el ruido total usando el ruido medido del amplificador es de 238μg/rt-Hz, un ruido más bajo que el de diseños encontrados en la literatura con sensores con una sensibilidad similar. El s, [CATALÀ] Aquesta tesi descriu el procés de disseny, la implementació i els resultats de les simulacions i les mesures de dos circuits de condicionament de senyal per ser usats amb dos sensors d'acceleració monolítics fabricats en el procés post-CMOS surface micromachining basat en isotropic wet etching en tecnologia IHP SiGe 0,25 μm. El primer disseny s'ha implementat amb un sensor de 50 fF de z-axis, mentre que el segon s'ha implementat, a més a més d'aquest mateix sensor, amb un segon sensor de 200 fF. El mètode utilitzat ha sigut el de sensat de Voltatge en Temps Continu (CTV) implementat de dues maneres. El primer disseny implementa el sensat CTV utilitzant una topologia en llaç obert, mentre que el segon disseny implementa el sensat CTV mitjançant un amplificador en llaç tancat i un reset amb baix duty-cycle. En ambdós dissenys, s'ha usat estabilització chopper per a eliminar offset DC i soroll Flicker, fent treballar els dos dissenys per sobre de la freqüència colze de soroll per tal d'obtenir el mínim soroll: soroll tèrmic. L'objectiu durant el disseny dels dos circuits ha sigut el de dissenyar dos circuits de condicionament amb un soroll tèrmic igual o menor al soroll Brownià del sensor capacitiu per tal de fer que el soroll dominant sigui el provinent del sensor. Això ha sigut possible gràcies a un profund estudi del soroll i l'optimització de les dimensions dels transistors que tenen una major influència: el parell de transistors d'entrada. En els dos casos, s'han elaborat equacions que relacionen la capacitat al node d'entrada amb el soroll, i els valors finalment usats han sigut obtinguts utilitzant el software de disseny seguint les hipòtesis marcades per les expressions obtingudes. El primer disseny ha sigut fabricat i el soroll total usant el soroll mesurat de l'amplificador és de 238μg/rt-Hz, un soroll més baix que dissenys trobats a la literatura amb sensors amb una sensitivitat similar. El segon disseny no s'ha fabricat encara, però les simulacions

[ANGLÈS] LISA and LISA Pathfinder missions demand that magnetic field meets low noise, low frequency conditions. Given Pathfinder's scientific requirments, this work wants to achieve a magnetic field with 1nt/sqrt(Hz) in the 1mHz to 30mHz band. A PID controller is needed to achieve the noise requirement, as well as an interpolation to know magnetic field by using near point data. The control also requires magnetic field generation, which will be done with a coil and a current source. In this work, a current source providing up to 0.5A has been designed in order to create magnetic field with the same noise and frequency requirments. Two different interpolation methods are proposed. Finally, PID's noise reduction efficacy and magnetometer's inner noise limitation will be analyzed., [CASTELLÀ] Las misiones LISA y LISA Pathfinder exigen al campo magnético condiciones de bajo ruido a baja frecuencia. Tomando como punto de partida los requisitios de Pathfinder, se quiere llegar a obtener un campo magnético con 1nT por raíz de hercio entre 1mHz y 30 mHz. Serán necesarios un control PID para llegar al requisito de ruido así como una interpolación para determinar el camp magnético a partir de la medida en puntos del entorno. Para controlar campo magnético también se tendrá que poder generarlo mediante fuenta de corriente y una bobina. En este trabajo se ha diseñado una fuente de corriente de hasta 0.5A para generar campo magnético con los mismos requisitos de ruido y frecuencia. Se han propuesto también dos métodos para la interpolación de campo magnético. Por último, se analiza la efectividad del PID para reducir ruido a baja frecuencia i la limitación impuesta por el ruido interno de los magnetómetros., [CATALA] Les missions LISA i LISA Pathfinder imposen al camp magnètic condicions de baix soroll a baixa freqüència. Partint dels requisits de Pathfinder, es vol arribar a aconseguir un camp magnètic amb 1nT per arrel d'Hertz entre 1mHz i 30mHz. Faran falta un control PID per aconseguir el requisit de soroll i una interpolació per determinar el camp magnètic a partir de la mesura en punts propers. Per controlar el camp magnètic també caldrà poder-ne generar amb una font de corrent i una bobina. En aquest treball s'ha dissenyat una font de corrent de fins a 0.5A per generar camp magnètic amb els mateixos requisits de soroll i freqüència. Dos mètodes diferents són proposats per a la interpolació. Finalment, s'analitza l'efectivitat del control PID per reduir soroll a baixa freqüència i la limitació imposada pel soroll intern dels magnetòmetres.

In this paper, we propose a discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather than opamps, thus being compatible with digital nanoscale technology. In the voltage-sampling mode, the gm-cell is bypassed so the filter is fully passive. A 7th-order filter prototype operating at 800 MS/s sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth of this filter is programmable between 400 kHz to 30 MHz with 100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the averaged spot noise is 4.57 nV/$surd$ Hz. It consumes 2 mW at 1.2 V and occupies 0.42 mm 2., Microelectronics, Electrical Engineering, Mathematics and Computer Science

During Phase II our team has tackled the main challenges related to the demonstration of low noise and high-frequency miniaturized aluminum nitride (AlN)-based frequency sources. Given the Phase I demonstration by our team, we have especially focused on understanding the noise sources in our oscillators and identifying new methods to evade phase noise., Sponsored in part by DARPA.

Low noise image sensors can see images by just a few photons have a wide application in both the scientific and economic fields. This thesis presents a design of a 16*16 pixels CMOS image sensor with a target noise level in the order of 0.5 electrons RMS in 0.18?m technology, which has a potential to catch a large amount of low light imaging market. First the novel 5T pinned photodiode low noise pixel is shown as well as the method cycling pMOS transistor well voltage between accumulation and inversion to shape the spectrum of flicker noise like white noise and to be decreased by oversampling. Then the readout circuitry with the sigma-delta ADCs and bidirectional digital counters are described. Correlated double sampling and oversampling technology are executed to decrease the quantization noise and thermal noise. At last, the system simulation, noise simulation results are given as well as the PCB test system., Microelectronics, Microelectronics & Computer Engineering, Electrical Engineering, Mathematics and Computer Science

Multi-threshold CMOS (MTCMOS) is commonly used for suppressing leakage currents in idle integrated circuits. Power and ground distribution network noise produced during SLEEP to ACTIVE mode transitions is an important reliability concern in MTCMOS circuits. Sleep signal slew rate modulation techniques for suppressing mode-transition noise are explored in this paper. A triple-phase sleep signal slew rate modulation (TPS) technique with a novel digital sleep signal generator is proposed. Reactivation time, mode-transition energy consumption, leakage power consumption, and layout area of different MTCMOS circuits are characterized under an equal-noise constraint. Influences of within-die and die-to-die parameter variations on the reactivation noise, time, and energy consumption of sleep signal slew rate modulated MTCMOS circuits are evaluated with a process imperfections aware robustness metric. The proposed triple-phase sleep signal slew rate modulation technique enhances the tolerance to process parameter fluctuations by up to 183.1x as compared to various alternative MTCMOS noise suppression techniques in a UMC 80-nm CMOS technology.

Multi-threshold CMOS (MTCMOS) is commonly used for suppressing leakage currents in idle integrated circuits. Power and ground distribution network noise produced during SLEEP to ACTIVE mode transitions is an important reliability concern in MTCMOS circuits. Sleep signal slew rate modulation techniques for suppressing mode-transition noise are explored in this paper. A triple-phase sleep signal slew rate modulation (TPS) technique with a novel digital sleep signal generator is proposed. Reactivation time, mode-transition energy consumption, leakage power consumption, and layout area of different MTCMOS circuits are characterized under an equal-noise constraint. Influences of within-die and die-to-die parameter variations on the reactivation noise, time, and energy consumption of sleep signal slew rate modulated MTCMOS circuits are evaluated with a process imperfections aware robustness metric. The proposed triple-phase sleep signal slew rate modulation technique enhances the tolerance to process parameter fluctuations by up to 183.1x as compared to various alternative MTCMOS noise suppression techniques in a UMC 80-nm CMOS technology.

Low noise image sensors can see images by just a few photons have a wide application in both the scientific and economic fields. This thesis presents a design of a 16*16 pixels CMOS image sensor with a target noise level in the order of 0.5 electrons RMS in 0.18?m technology, which has a potential to catch a large amount of low light imaging market. First the novel 5T pinned photodiode low noise pixel is shown as well as the method cycling pMOS transistor well voltage between accumulation and inversion to shape the spectrum of flicker noise like white noise and to be decreased by oversampling. Then the readout circuitry with the sigma-delta ADCs and bidirectional digital counters are described. Correlated double sampling and oversampling technology are executed to decrease the quantization noise and thermal noise. At last, the system simulation, noise simulation results are given as well as the PCB test system., Microelectronics, Microelectronics & Computer Engineering, Electrical Engineering, Mathematics and Computer Science

Multi-threshold CMOS (MTCMOS) is commonly used for suppressing leakage currents in idle integrated circuits. Power and ground distribution network noise produced during SLEEP to ACTIVE mode transitions is an important reliability concern in MTCMOS circuits. Sleep signal slew rate modulation techniques for suppressing mode-transition noise are explored in this paper. A triple-phase sleep signal slew rate modulation (TPS) technique with a novel digital sleep signal generator is proposed. Reactivation time, mode-transition energy consumption, leakage power consumption, and layout area of different MTCMOS circuits are characterized under an equal-noise constraint. Influences of within-die and die-to-die parameter variations on the reactivation noise, time, and energy consumption of sleep signal slew rate modulated MTCMOS circuits are evaluated with a process imperfections aware robustness metric. The proposed triple-phase sleep signal slew rate modulation technique enhances the tolerance to process parameter fluctuations by up to 183.1x as compared to various alternative MTCMOS noise suppression techniques in a UMC 80-nm CMOS technology.

This the final report for a one-year effort to develop a high frame-rate multi-scale camera for investigations of fine-scale auroral dynamics and induced beam-plasma instabilities in the high-latitude ionosphere. The scope of the project included development and field-testing of the instrument, as well as development of an image processing framework for extracting physical parameters from the recorded measurements. The optical architecture consisted of a low-noise scientific-grade CMOS sensor coupled to a 140-mm f/1 optic through a prompt-emission notch filter. This design provided meter-scale spatial resolution at 120-km stand-off distance over an 8x6 degree field-of-view. 16-bit sampling provided the large dynamic range required to observe the full range of variability in the aurora. A lower resolution wide-field sensor provided contextual information and the acquisition trigger for the CMOS sensor. Triggering was accomplished via real-time analysis of intensity and motions of targets within the field. Initial observations from the Sondrestrom, Greenland, ionospheric research facility have provided compelling proof-of-concept in support of a broader science program, as discussed in this report., The original document contains color images.

A digital sun sensor is superior to an analog sun sensor in aspects of resolution, albedo immunity, and integration. The proposed Micro-Digital Sun Sensor (µDSS) is an autonomous digital sun sensor which is implemented by means of a CMOS image sensor, which is named APS+. The µDSS is designed specifically for micro-satellite application which addresses for low power and high accuracy. The APS+ significantly reduces the power consumption by a profiling method and obtains low noise by a quadruple sampling method. Measurement results show that the µDSS achieves an accuracy of 0.01º with 21mW@10fps, which is 10 times less than the state of the art., Microelectronics & Computer Engineering, Electrical Engineering, Mathematics and Computer Science

NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-ß decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz. © 2011 Elsevier B.V.

The complete readout and biasing system for the MARE experiment in Milan is presented. The experiment aims at a direct measurement of the neutrino mass, and is based on an array of microcalorimeters coupled to semiconductor thermistors. The readout is based on JFETs operated inside the cryostat at cold (130 K), to buffer the voltage signal from the thermistors. The sources of the JFETs are fed into second stage amplifiers with very low noise (less than 0.5 nV/Hz−−√ white noise) and programmable high gain. The outputs are then processed by Bessel filters and acquired with a commercial DAQ system. Every 20 channels, an additional group of 4 is used to amplify the ground reference from inside the cryostat; this common ground signal is then subtracted from each channel. This approach allows to recover a fully differential readout with a smaller number of cables with respect to the standard differential configuration. The detector bias is programmable in voltage and sign with 8-bit resolution. A test signal can be superimposed on the bias voltage, in order to test each channel individually. All the readout system is remotely programmable from a PC, coupled through optical fibers.

Envisioning novel fully monolithic fiber-optical devices, this dissertation investigates four fiber optical devices both, active and passive, that contribute to the goal of further integrating and miniaturizing fiber optics. An all phosphate glass fiber laser was designed in an effort to reduce laser intensity noise by reducing cavity losses and low mechanical strength that arise from intra-cavity fusion splices between silica fiber Bragg gratings (FBG) and phosphate active fiber in state of the art phosphate single frequency fiber lasers. Novel phosphate glass based FBGs have been fabricated utilizing high intensity laser pulses at 193 nm and a phase-mask. Net reflectivities of up to 70 % and a bandwidth of 50 pm have been achieved in the FBGs. The laser design comprised two of the novel FBGs and a short section of Er³⁺Yb³⁺ phosphate fiber to form a distributed Bragg reflector (DBR) laser. The performance of the new laser has been compared to a conventional phosphate fiber laser. Particular focus was put on the laser intensity noise due to its dependence on intra-cavity losses. Relative intensity noise (RIN) amplitudes of -80 dB/Hz have been measured for both lasers when operating at comparable output powers. For similar levels of absorbed pump power the relaxation oscillation frequencies (ROF) were shifted towards lower frequencies in the new laser. ExcessFBG scattering losses and mode-field miss-match between the active and passive fiber limited the output power of the new laser to 16 mW compared to 140 mW in the conventional laser. A monolithic all-phosphate glass fiber laser with up to 550 mW output power that is operating at a single longitudinal mode and exhibiting narrow linewidth is presented. The laser cavity has been formed by inscribing FBGs directly into heavily Er³⁺Yb³⁺ doped phosphate glass fiber using femtosecond laser pulses and a phase mask, completely eliminating the need for intra-cavity fusion splices. A linewidth of less than 60 kHz and relaxat

A digital sun sensor is superior to an analog sun sensor in aspects of resolution, albedo immunity, and integration. The proposed Micro-Digital Sun Sensor (µDSS) is an autonomous digital sun sensor which is implemented by means of a CMOS image sensor, which is named APS+. The µDSS is designed specifically for micro-satellite application which addresses for low power and high accuracy. The APS+ significantly reduces the power consumption by a profiling method and obtains low noise by a quadruple sampling method. Measurement results show that the µDSS achieves an accuracy of 0.01º with 21mW@10fps, which is 10 times less than the state of the art., Microelectronics & Computer Engineering, Electrical Engineering, Mathematics and Computer Science

NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-ß decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz. © 2011 Elsevier B.V.

The ability to accurately simulate rare high energy collisions such as those found in ionization and combustion reactions is important to the advancement of the study of non-equilibrium behavior of these phenomena. A major difficulty for modeling these systems with particle codes is that chain-branching reactions result in exponential growth regimes for certain species. This work considers the use of fractional collision models in place of statistically sampled collision models combined with merging of computational particles to reduce statistical noise while avoiding runaway computational cost., The original document contains color images. Presented at the International Symposium on Rarefied Gas Dynamics (28th) held in Zaragoza, Spain on 9-13 July 2012.

A very broadband distributed amplifier was designed using a 0.13-micrometer gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (PHEMT) process from TriQuint Semiconductor. The design and fabrication of this circuit was performed as part of the fall 2011 Johns Hopkins University Monolithic Microwave Integrated Circuit (MMIC) Design Course, taught by the author. The design approach is applicable to very broadband, low noise MMICs that could be used for a variety of radio frequency (RF) and microwave systems., The original document contains color images.

Photonic systems that transmit and process microwave-frequency analog signals have traditionally been encumbered by relatively large signal distortion and noise. Optical phase modulation (PM) and frequency modulation (FM) are promising techniques that can improve system performance. In this dissertation, I discuss an optical filtering approach to demodulation of PM and FM signals, which does not rely on high frequency electronics, and which scales in linearity with increasing photonic integration. I present an analytical model, lter designs and simulations, and experimental results using planar lightwave circuit (PLC) lters and FM distributed Bragg re ec- tor (DBR) lasers. The linearity of the PM and FM photonic links exceed that of the current state-of-the-art.

Two-port film plate acoustic resonators (FPAR) devices operating on the lowest order symmetric Lamb wave mode (S0) in C-oriented AlN membranes on Si were fabricated and tested for their power handling capabilities in a feedback-loop power oscillator circuit. The FPAR was operated at an incident power level of 24 dBm for several weeks without performance degradation. Its flicker noise constant was calculated from close-in phase noise data as αR=2.1×10^−36/Hz. The results indicate that IC-compatible S0 FPARs are well suited for integrated microwave oscillators with thermal noise floor (TNF) levels below −175 dBc/Hz., VR "Thin Film Guided Microacoustic Waves in Periodical Systems: Theory and Applications"